View UPD161623_1966200.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd161623 528 output tft-lcd source driver with ram data sheet document no. s15817ej2v0ds00 (2nd edition) date published july 2002 ns cp(k) printed in japan the mark shows major revised points. description the pd161623 is a tft-lcd source driver that includes display ram. this driver has 528 outputs, a display ram capacity of 760,320 bits (176 pixels x 18 bits x 240 lines) and, can provide a 262,144-color display. features ? tft-lcd driver with on-chip display ram ? i/o circuit power supply voltage: 1.7 to 3.6 v ? logic power supply voltage: 2.5 to 3.6 v ? driver power supply voltage: 4.3 to 5.5 v ? display ram: 176 x 18 x 240 bits ? driver outputs: 528 output ? cpu interface: serial, 18-bit/16-bit parallel interface selectable ? colors: 262,144 colors/pixel ? on-chip vcom generator ? on-chip timing generator ? on-chip oscillator ordering information part number package pd161623p chip remark purchasing the above chip entails the exchange of documents such as a separate memorandum on product quality, so please contact one of our sales representatives.
data sheet s15817ej2v0ds 2 pd161623 1. block diagram lcd drive circuit display data ram (176 x 18 x 240 bits) y 1 decoder level shifter (2.5 v 5 v) display data latch ram controller internal timing generator command decoder address decoder / controller data register vcom generator i/o buffer gate control gray scale generator lcd timing control bgr oscillator calibrator y 527 y 4 y 3 y 2 y 528 rs /rd(e) /wr(r, /w) d 0 to d 17 /reset c86 tout 0 to tout 17 tosco gclk gstb goe 1 vcom goe 2 v 0 to v 5 ps control dcon lpmp vcout1 v ce v cd2 v cd11 v cd12 tbgr /cs psx 0 cstb op 0 to op 7 v rh v rl1 v rl2 v dd1 v dd2 v ss cvph cvpl cvnh cvnl osc out osc sel osc in d/a converter bgrin dac 0 to dac 7 vcomr vcout2 dtx psx 1 tstrtst tstvihl rgonp tbsel1 v dd1(mode) v dd2(mode) fbr sel tosci toscseli toscselo si scl tbsel2 v ss(mode) remark /xxx indicates active low signal.
data sheet s15817ej2v0ds 3 pd161623 2. pin configuration (pad layout) chip size: 3.75 x 23.00 mm 2 typ. bump size (output): 35 x 94 m 2 typ. bump size (input & dummy): 80 x 86 m 2 typ. alignment mark (mark center, unit: m) xy m1 ? 1690 11315 m2 ? 1690 ? 11315 y(+ x(+ 41.5 m 41.5 m 130 m 204 60 72 72 204 60 72 72 1 737 734 733 190 189 186 185 alignment mark reference (unit: m)
data sheet s15817ej2v0ds 4 pd161623 table 2?1. pad layout (1/4) pad pad name pad pad pad name pad pad pad name pad no. type x y no. type x y no. type x y 1 dummy b -1749.00 11000.00 71 rs b -1749.00 2600.00 141 op0 b -1749.00 -5800.00 2 dummy b -1749.00 10880.00 72 /wr ( r, /w ) b -1749.00 2480.00 142 op1 b -1749.00 -5920.00 3 dummy b -1749.00 10760.00 73 /rd ( e ) b -1749.00 2360.00 143 op2 b -1749.00 -6040.00 4 dummy b -1749.00 10640.00 74 vss ( mode ) b -1749.00 2240.00 144 op3 b -1749.00 -6160.00 5 dummy b -1749.00 10520.00 75 si b -1749.00 2120.00 145 op4 b -1749.00 -6280.00 6 dummy b -1749.00 10400.00 76 scl b -1749.00 2000.00 146 op5 b -1749.00 -6400.00 7 dummy b -1749.00 10280.00 77 vdd1 b -1749.00 1880.00 147 op6 b -1749.00 -6520.00 8 dummy b -1749.00 10160.00 78 psx1 b -1749.00 1760.00 148 op7 b -1749.00 -6640.00 9 dummy b -1749.00 10040.00 79 vss ( mode ) b -1749.00 1640.00 149 gstb b -1749.00 -6760.00 10 dummy b -1749.00 9920.00 80 psx0 b -1749.00 1520.00 150 gclk b -1749.00 -6880.00 11 dummy b -1749.00 9800.00 81 vdd1 ( mode ) b -1749.00 1400.00 151 goe1 b -1749.00 -7000.00 12 dummy b -1749.00 9680.00 82 c86 b -1749.00 1280.00 152 goe2 b -1749.00 -7120.00 13 dummy b -1749.00 9560.00 83 vss ( mode ) b -1749.00 1160.00 153 dummy b -1749.00 -7240.00 14 dummy b -1749.00 9440.00 84 dtx b -1749.00 1040.00 154 dummy b -1749.00 -7360.00 15 dummy b -1749.00 9320.00 85 vdd1 ( mode ) b -1749.00 920.00 155 dummy b -1749.00 -7480.00 16 dummy b -1749.00 9200.00 86 vce b -1749.00 800.00 156 dummy b -1749.00 -7600.00 17 tout17 b -1749.00 9080.00 87 vcd2 b -1749.00 680.00 157 dummy b -1749.00 -7720.00 18 tout16 b -1749.00 8960.00 88 vcd12 b -1749.00 560.00 158 dummy b -1749.00 -7840.00 19 tout15 b -1749.00 8840.00 89 vcd11 b -1749.00 440.00 159 dummy b -1749.00 -7960.00 20 tout14 b -1749.00 8720.00 90 lpmp b -1749.00 320.00 160 dummy b -1749.00 -8080.00 21 tout13 b -1749.00 8600.00 91 rgonp b -1749.00 200.00 161 dummy b -1749.00 -8200.00 22 tout12 b -1749.00 8480.00 92 dcon b -1749.00 80.00 162 dummy b -1749.00 -8320.00 23 tout11 b -1749.00 8360.00 93 vcout2 b -1749.00 -40.00 163 dummy b -1749.00 -8440.00 24 tout10 b -1749.00 8240.00 94 vss b -1749.00 -160.00 164 dummy b -1749.00 -8560.00 25 tout9 b -1749.00 8120.00 95 vdd1 b -1749.00 -280.00 165 dummy b -1749.00 -8680.00 26 tout8 b -1749.00 8000.00 96 vdd2 b -1749.00 -400.00 166 dummy b -1749.00 -8800.00 27 tout7 b -1749.00 7880.00 97 vss b -1749.00 -520.00 167 dummy b -1749.00 -8920.00 28 tout6 b -1749.00 7760.00 98 vss b -1749.00 -640.00 168 dummy b -1749.00 -9040.00 29 tout5 b -1749.00 7640.00 99 cvnl b -1749.00 -760.00 169 dummy b -1749.00 -9160.00 30 tout4 b -1749.00 7520.00 100 cvnh b -1749.00 -880.00 170 dummy b -1749.00 -9280.00 31 tout3 b -1749.00 7400.00 101 cvpl b -1749.00 -1000.00 171 dummy b -1749.00 -9400.00 32 tout2 b -1749.00 7280.00 102 cvph b -1749.00 -1120.00 172 dummy b -1749.00 -9520.00 33 tout1 b -1749.00 7160.00 103 vs b -1749.00 -1240.00 173 dummy b -1749.00 -9640.00 34 tout0 b -1749.00 7040.00 104 vs b -1749.00 -1360.00 174 dummy b -1749.00 -9760.00 35 vss ( mode ) b -1749.00 6920.00 105 vss b -1749.00 -1480.00 175 dummy b -1749.00 -9880.00 36 tstvihl b -1749.00 6800.00 106 vcout1 b -1749.00 -1600.00 176 dummy b -1749.00 -10000.00 37 tstrtst b -1749.00 6680.00 107 vcout1 b -1749.00 -1720.00 177 dummy b -1749.00 -10120.00 38 toscselo b -1749.00 6560.00 108 vdd2 b -1749.00 -1840.00 178 dummy b -1749.00 -10240.00 39 toscseli b -1749.00 6440.00 109 vdd2 b -1749.00 -1960.00 179 dummy b -1749.00 -10360.00 40 tosci b -1749.00 6320.00 110 vcom b -1749.00 -2080.00 180 dummy b -1749.00 -10480.00 41 tosco b -1749.00 6200.00 111 dummy b -1749.00 -2200.00 181 dummy b -1749.00 -10600.00 42 vdd2 ( mode ) b -1749.00 6080.00 112 dummy b -1749.00 -2320.00 182 dummy b -1749.00 -10720.00 43 oscsel b -1749.00 5960.00 113 vss ( mode ) b -1749.00 -2440.00 183 dummy b -1749.00 -10840.00 44 vss ( mode ) b -1749.00 5840.00 114 vcomr b -1749.00 -2560.00 184 dummy b -1749.00 -10960.00 45 oscout b -1749.00 5720.00 115 bgrin b -1749.00 -2680.00 185 dummy b -1749.00 -11080.00 46 vss ( mode ) b -1749.00 5600.00 116 vdd2 ( mode ) b -1749.00 -2800.00 186 dummy b -1350.00 -11374.00 47 oscin b -1749.00 5480.00 117 fbrsel b -1749.00 -2920.00 187 dummy b -450.00 -11374.00 48 vss ( mode ) b -1749.00 5360.00 118 vss ( mode ) b -1749.00 -3040.00 188 dummy b 450.00 -11374.00 49 cstb b -1749.00 5240.00 119 vrh b -1749.00 -3160.00 189 dummy b 1350.00 -11374.00 50 d17 b -1749.00 5120.00 120 v0 b -1749.00 -3280.00 190 dummy a 1745.00 -11302.50 51 d16 b -1749.00 5000.00 121 v1 b -1749.00 -3400.00 191 dummy a 1745.00 -11252.50 52 d15 b -1749.00 4880.00 122 v2 b -1749.00 -3520.00 192 dummy a 1745.00 -11201.50 53 d14 b -1749.00 4760.00 123 v3 b -1749.00 -3640.00 193 y528 a 1745.00 -11140.50 54 d13 b -1749.00 4640.00 124 v4 b -1749.00 -3760.00 194 y527 a 1615.00 -11099.00 55 d12 b -1749.00 4520.00 125 v5 b -1749.00 -3880.00 195 y526 a 1745.00 -11057.50 56 d11 b -1749.00 4400.00 126 vrl1 b -1749.00 -4000.00 196 y525 a 1615.00 -11016.00 57 d10 b -1749.00 4280.00 127 vrl2 b -1749.00 -4120.00 197 y524 a 1745.00 -10974.50 58 d9 b -1749.00 4160.00 128 vss ( mode ) b -1749.00 -4240.00 198 y523 a 1615.00 -10933.00 59 d8 b -1749.00 4040.00 129 tbsel1 b -1749.00 -4360.00 199 y522 a 1745.00 -10891.50 60 d7 b -1749.00 3920.00 130 tbsel2 b -1749.00 -4480.00 200 y521 a 1615.00 -10850.00 61 d6 b -1749.00 3800.00 131 tbgr b -1749.00 -4600.00 201 y520 a 1745.00 -10808.50 62 d5 b -1749.00 3680.00 132 dac7 b -1749.00 -4720.00 202 y519 a 1615.00 -10767.00 63 d4 b -1749.00 3560.00 133 dac6 b -1749.00 -4840.00 203 y518 a 1745.00 -10725.50 64 d3 b -1749.00 3440.00 134 dac5 b -1749.00 -4960.00 204 y517 a 1615.00 -10684.00 65 d2 b -1749.00 3320.00 135 dac4 b -1749.00 -5080.00 205 y516 a 1745.00 -10642.50 66 d1 b -1749.00 3200.00 136 dac3 b -1749.00 -5200.00 206 y515 a 1615.00 -10601.00 67 d0 b -1749.00 3080.00 137 dac2 b -1749.00 -5320.00 207 y514 a 1745.00 -10559.50 68 vss ( mode ) b -1749.00 2960.00 138 dac1 b -1749.00 -5440.00 208 y513 a 1615.00 -10518.00 69 /cs b -1749.00 2840.00 139 dac0 b -1749.00 -5560.00 209 y512 a 1745.00 -10476.50 70 /reset b -1749.00 2720.00 140 vss(mode) b -1749.00 -5680.00 210 y511 a 1615.00 -10435.00 pad layout [ m] pad layout [ m] pad layout [ m]
data sheet s15817ej2v0ds 5 pd161623 table 2?1. pad layout (2/4) pad pad name pad pad pad name pad pad pad name pad no. type x y no. type x y no. type x y 211 y510 a 1745.00 -10393.50 281 y440 a 1745.00 -7488.50 351 y370 a 1745.00 -4583.50 212 y509 a 1615.00 -10352.00 282 y439 a 1615.00 -7447.00 352 y369 a 1615.00 -4542.00 213 y508 a 1745.00 -10310.50 283 y438 a 1745.00 -7405.50 353 y368 a 1745.00 -4500.50 214 y507 a 1615.00 -10269.00 284 y437 a 1615.00 -7364.00 354 y367 a 1615.00 -4459.00 215 y506 a 1745.00 -10227.50 285 y436 a 1745.00 -7322.50 355 y366 a 1745.00 -4417.50 216 y505 a 1615.00 -10186.00 286 y435 a 1615.00 -7281.00 356 y365 a 1615.00 -4376.00 217 y504 a 1745.00 -10144.50 287 y434 a 1745.00 -7239.50 357 y364 a 1745.00 -4334.50 218 y503 a 1615.00 -10103.00 288 y433 a 1615.00 -7198.00 358 y363 a 1615.00 -4293.00 219 y502 a 1745.00 -10061.50 289 y432 a 1745.00 -7156.50 359 y362 a 1745.00 -4251.50 220 y501 a 1615.00 -10020.00 290 y431 a 1615.00 -7115.00 360 y361 a 1615.00 -4210.00 221 y500 a 1745.00 -9978.50 291 y430 a 1745.00 -7073.50 361 y360 a 1745.00 -4168.50 222 y499 a 1615.00 -9937.00 292 y429 a 1615.00 -7032.00 362 y359 a 1615.00 -4127.00 223 y498 a 1745.00 -9895.50 293 y428 a 1745.00 -6990.50 363 y358 a 1745.00 -4085.50 224 y497 a 1615.00 -9854.00 294 y427 a 1615.00 -6949.00 364 y357 a 1615.00 -4044.00 225 y496 a 1745.00 -9812.50 295 y426 a 1745.00 -6907.50 365 y356 a 1745.00 -4002.50 226 y495 a 1615.00 -9771.00 296 y425 a 1615.00 -6866.00 366 y355 a 1615.00 -3961.00 227 y494 a 1745.00 -9729.50 297 y424 a 1745.00 -6824.50 367 y354 a 1745.00 -3919.50 228 y493 a 1615.00 -9688.00 298 y423 a 1615.00 -6783.00 368 y353 a 1615.00 -3878.00 229 y492 a 1745.00 -9646.50 299 y422 a 1745.00 -6741.50 369 y352 a 1745.00 -3836.50 230 y491 a 1615.00 -9605.00 300 y421 a 1615.00 -6700.00 370 y351 a 1615.00 -3795.00 231 y490 a 1745.00 -9563.50 301 y420 a 1745.00 -6658.50 371 y350 a 1745.00 -3753.50 232 y489 a 1615.00 -9522.00 302 y419 a 1615.00 -6617.00 372 y349 a 1615.00 -3712.00 233 y488 a 1745.00 -9480.50 303 y418 a 1745.00 -6575.50 373 y348 a 1745.00 -3670.50 234 y487 a 1615.00 -9439.00 304 y417 a 1615.00 -6534.00 374 y347 a 1615.00 -3629.00 235 y486 a 1745.00 -9397.50 305 y416 a 1745.00 -6492.50 375 y346 a 1745.00 -3587.50 236 y485 a 1615.00 -9356.00 306 y415 a 1615.00 -6451.00 376 y345 a 1615.00 -3546.00 237 y484 a 1745.00 -9314.50 307 y414 a 1745.00 -6409.50 377 y344 a 1745.00 -3504.50 238 y483 a 1615.00 -9273.00 308 y413 a 1615.00 -6368.00 378 y343 a 1615.00 -3463.00 239 y482 a 1745.00 -9231.50 309 y412 a 1745.00 -6326.50 379 y342 a 1745.00 -3421.50 240 y481 a 1615.00 -9190.00 310 y411 a 1615.00 -6285.00 380 y341 a 1615.00 -3380.00 241 y480 a 1745.00 -9148.50 311 y410 a 1745.00 -6243.50 381 y340 a 1745.00 -3338.50 242 y479 a 1615.00 -9107.00 312 y409 a 1615.00 -6202.00 382 y339 a 1615.00 -3297.00 243 y478 a 1745.00 -9065.50 313 y408 a 1745.00 -6160.50 383 y338 a 1745.00 -3255.50 244 y477 a 1615.00 -9024.00 314 y407 a 1615.00 -6119.00 384 y337 a 1615.00 -3214.00 245 y476 a 1745.00 -8982.50 315 y406 a 1745.00 -6077.50 385 y336 a 1745.00 -3172.50 246 y475 a 1615.00 -8941.00 316 y405 a 1615.00 -6036.00 386 y335 a 1615.00 -3131.00 247 y474 a 1745.00 -8899.50 317 y404 a 1745.00 -5994.50 387 y334 a 1745.00 -3089.50 248 y473 a 1615.00 -8858.00 318 y403 a 1615.00 -5953.00 388 y333 a 1615.00 -3048.00 249 y472 a 1745.00 -8816.50 319 y402 a 1745.00 -5911.50 389 y332 a 1745.00 -3006.50 250 y471 a 1615.00 -8775.00 320 y401 a 1615.00 -5870.00 390 y331 a 1615.00 -2965.00 251 y470 a 1745.00 -8733.50 321 y400 a 1745.00 -5828.50 391 y330 a 1745.00 -2923.50 252 y469 a 1615.00 -8692.00 322 y399 a 1615.00 -5787.00 392 y329 a 1615.00 -2882.00 253 y468 a 1745.00 -8650.50 323 y398 a 1745.00 -5745.50 393 y328 a 1745.00 -2840.50 254 y467 a 1615.00 -8609.00 324 y397 a 1615.00 -5704.00 394 y327 a 1615.00 -2799.00 255 y466 a 1745.00 -8567.50 325 y396 a 1745.00 -5662.50 395 y326 a 1745.00 -2757.50 256 y465 a 1615.00 -8526.00 326 y395 a 1615.00 -5621.00 396 y325 a 1615.00 -2716.00 257 y464 a 1745.00 -8484.50 327 y394 a 1745.00 -5579.50 397 y324 a 1745.00 -2674.50 258 y463 a 1615.00 -8443.00 328 y393 a 1615.00 -5538.00 398 y323 a 1615.00 -2633.00 259 y462 a 1745.00 -8401.50 329 y392 a 1745.00 -5496.50 399 y322 a 1745.00 -2591.50 260 y461 a 1615.00 -8360.00 330 y391 a 1615.00 -5455.00 400 y321 a 1615.00 -2550.00 261 y460 a 1745.00 -8318.50 331 y390 a 1745.00 -5413.50 401 y320 a 1745.00 -2508.50 262 y459 a 1615.00 -8277.00 332 y389 a 1615.00 -5372.00 402 y319 a 1615.00 -2467.00 263 y458 a 1745.00 -8235.50 333 y388 a 1745.00 -5330.50 403 y318 a 1745.00 -2425.50 264 y457 a 1615.00 -8194.00 334 y387 a 1615.00 -5289.00 404 y317 a 1615.00 -2384.00 265 y456 a 1745.00 -8152.50 335 y386 a 1745.00 -5247.50 405 y316 a 1745.00 -2342.50 266 y455 a 1615.00 -8111.00 336 y385 a 1615.00 -5206.00 406 y315 a 1615.00 -2301.00 267 y454 a 1745.00 -8069.50 337 y384 a 1745.00 -5164.50 407 y314 a 1745.00 -2259.50 268 y453 a 1615.00 -8028.00 338 y383 a 1615.00 -5123.00 408 y313 a 1615.00 -2218.00 269 y452 a 1745.00 -7986.50 339 y382 a 1745.00 -5081.50 409 y312 a 1745.00 -2176.50 270 y451 a 1615.00 -7945.00 340 y381 a 1615.00 -5040.00 410 y311 a 1615.00 -2135.00 271 y450 a 1745.00 -7903.50 341 y380 a 1745.00 -4998.50 411 y310 a 1745.00 -2093.50 272 y449 a 1615.00 -7862.00 342 y379 a 1615.00 -4957.00 412 y309 a 1615.00 -2052.00 273 y448 a 1745.00 -7820.50 343 y378 a 1745.00 -4915.50 413 y308 a 1745.00 -2010.50 274 y447 a 1615.00 -7779.00 344 y377 a 1615.00 -4874.00 414 y307 a 1615.00 -1969.00 275 y446 a 1745.00 -7737.50 345 y376 a 1745.00 -4832.50 415 y306 a 1745.00 -1927.50 276 y445 a 1615.00 -7696.00 346 y375 a 1615.00 -4791.00 416 y305 a 1615.00 -1886.00 277 y444 a 1745.00 -7654.50 347 y374 a 1745.00 -4749.50 417 y304 a 1745.00 -1844.50 278 y443 a 1615.00 -7613.00 348 y373 a 1615.00 -4708.00 418 y303 a 1615.00 -1803.00 279 y442 a 1745.00 -7571.50 349 y372 a 1745.00 -4666.50 419 y302 a 1745.00 -1761.50 280 y441 a 1615 . 00 - 7530 . 00 350 y371 a 1615 . 00 - 4625 . 00 420 y301 a 1615 . 00 - 1720 . 00 pad layout [
data sheet s15817ej2v0ds 6 pd161623 table 2 ? 1. pad layout (3/4) pad pad name pad pad pad name pad pad pad name pad no. type x y no. type x y no. type x y 421 y300 a 1745.00 -1678.50 491 y240 a 1745.00 1226.50 561 y170 a 1745.00 4131.50 422 y299 a 1615.00 -1637.00 492 y239 a 1615.00 1268.00 562 y169 a 1615.00 4173.00 423 y298 a 1745.00 -1595.50 493 y238 a 1745.00 1309.50 563 y168 a 1745.00 4214.50 424 y297 a 1615.00 -1554.00 494 y237 a 1615.00 1351.00 564 y167 a 1615.00 4256.00 425 y296 a 1745.00 -1512.50 495 y236 a 1745.00 1392.50 565 y166 a 1745.00 4297.50 426 y295 a 1615.00 -1471.00 496 y235 a 1615.00 1434.00 566 y165 a 1615.00 4339.00 427 y294 a 1745.00 -1429.50 497 y234 a 1745.00 1475.50 567 y164 a 1745.00 4380.50 428 y293 a 1615.00 -1388.00 498 y233 a 1615.00 1517.00 568 y163 a 1615.00 4422.00 429 y292 a 1745.00 -1346.50 499 y232 a 1745.00 1558.50 569 y162 a 1745.00 4463.50 430 y291 a 1615.00 -1305.00 500 y231 a 1615.00 1600.00 570 y161 a 1615.00 4505.00 431 y290 a 1745.00 -1263.50 501 y230 a 1745.00 1641.50 571 y160 a 1745.00 4546.50 432 y289 a 1615.00 -1222.00 502 y229 a 1615.00 1683.00 572 y159 a 1615.00 4588.00 433 y288 a 1745.00 -1180.50 503 y228 a 1745.00 1724.50 573 y158 a 1745.00 4629.50 434 y287 a 1615.00 -1139.00 504 y227 a 1615.00 1766.00 574 y157 a 1615.00 4671.00 435 y286 a 1745.00 -1097.50 505 y226 a 1745.00 1807.50 575 y156 a 1745.00 4712.50 436 y285 a 1615.00 -1056.00 506 y225 a 1615.00 1849.00 576 y155 a 1615.00 4754.00 437 y284 a 1745.00 -1014.50 507 y224 a 1745.00 1890.50 577 y154 a 1745.00 4795.50 438 y283 a 1615.00 -973.00 508 y223 a 1615.00 1932.00 578 y153 a 1615.00 4837.00 439 y282 a 1745.00 -931.50 509 y222 a 1745.00 1973.50 579 y152 a 1745.00 4878.50 440 y281 a 1615.00 -890.00 510 y221 a 1615.00 2015.00 580 y151 a 1615.00 4920.00 441 y280 a 1745.00 -848.50 511 y220 a 1745.00 2056.50 581 y150 a 1745.00 4961.50 442 y279 a 1615.00 -807.00 512 y219 a 1615.00 2098.00 582 y149 a 1615.00 5003.00 443 y278 a 1745.00 -765.50 513 y218 a 1745.00 2139.50 583 y148 a 1745.00 5044.50 444 y277 a 1615.00 -724.00 514 y217 a 1615.00 2181.00 584 y147 a 1615.00 5086.00 445 y276 a 1745.00 -682.50 515 y216 a 1745.00 2222.50 585 y146 a 1745.00 5127.50 446 y275 a 1615.00 -641.00 516 y215 a 1615.00 2264.00 586 y145 a 1615.00 5169.00 447 y274 a 1745.00 -599.50 517 y214 a 1745.00 2305.50 587 y144 a 1745.00 5210.50 448 y273 a 1615.00 -558.00 518 y213 a 1615.00 2347.00 588 y143 a 1615.00 5252.00 449 y272 a 1745.00 -516.50 519 y212 a 1745.00 2388.50 589 y142 a 1745.00 5293.50 450 y271 a 1615.00 -475.00 520 y211 a 1615.00 2430.00 590 y141 a 1615.00 5335.00 451 y270 a 1745.00 -433.50 521 y210 a 1745.00 2471.50 591 y140 a 1745.00 5376.50 452 y269 a 1615.00 -392.00 522 y209 a 1615.00 2513.00 592 y139 a 1615.00 5418.00 453 y268 a 1745.00 -350.50 523 y208 a 1745.00 2554.50 593 y138 a 1745.00 5459.50 454 y267 a 1615.00 -309.00 524 y207 a 1615.00 2596.00 594 y137 a 1615.00 5501.00 455 y266 a 1745.00 -267.50 525 y206 a 1745.00 2637.50 595 y136 a 1745.00 5542.50 456 y265 a 1615.00 -226.00 526 y205 a 1615.00 2679.00 596 y135 a 1615.00 5584.00 457 y264 a 1745.00 -184.50 527 y204 a 1745.00 2720.50 597 y134 a 1745.00 5625.50 458 dummy a 1615.00 -143.00 528 y203 a 1615.00 2762.00 598 y133 a 1615.00 5667.00 459 dummy a 1745.00 -101.50 529 y202 a 1745.00 2803.50 599 y132 a 1745.00 5708.50 460 dummy a 1615.00 -60.00 530 y201 a 1615.00 2845.00 600 y131 a 1615.00 5750.00 461 dummy a 1745.00 -18.50 531 y200 a 1745.00 2886.50 601 y130 a 1745.00 5791.50 462 dummy a 1615.00 23.00 532 y199 a 1615.00 2928.00 602 y129 a 1615.00 5833.00 463 dummy a 1745.00 64.50 533 y198 a 1745.00 2969.50 603 y128 a 1745.00 5874.50 464 dummy a 1615.00 106.00 534 y197 a 1615.00 3011.00 604 y127 a 1615.00 5916.00 465 dummy a 1745.00 147.50 535 y196 a 1745.00 3052.50 605 y126 a 1745.00 5957.50 466 dummy a 1615.00 189.00 536 y195 a 1615.00 3094.00 606 y125 a 1615.00 5999.00 467 dummy a 1745.00 230.50 537 y194 a 1745.00 3135.50 607 y124 a 1745.00 6040.50 468 y263 a 1615.00 272.00 538 y193 a 1615.00 3177.00 608 y123 a 1615.00 6082.00 469 y262 a 1745.00 313.50 539 y192 a 1745.00 3218.50 609 y122 a 1745.00 6123.50 470 y261 a 1615.00 355.00 540 y191 a 1615.00 3260.00 610 y121 a 1615.00 6165.00 471 y260 a 1745.00 396.50 541 y190 a 1745.00 3301.50 611 y120 a 1745.00 6206.50 472 y259 a 1615.00 438.00 542 y189 a 1615.00 3343.00 612 y119 a 1615.00 6248.00 473 y258 a 1745.00 479.50 543 y188 a 1745.00 3384.50 613 y118 a 1745.00 6289.50 474 y257 a 1615.00 521.00 544 y187 a 1615.00 3426.00 614 y117 a 1615.00 6331.00 475 y256 a 1745.00 562.50 545 y186 a 1745.00 3467.50 615 y116 a 1745.00 6372.50 476 y255 a 1615.00 604.00 546 y185 a 1615.00 3509.00 616 y115 a 1615.00 6414.00 477 y254 a 1745.00 645.50 547 y184 a 1745.00 3550.50 617 y114 a 1745.00 6455.50 478 y253 a 1615.00 687.00 548 y183 a 1615.00 3592.00 618 y113 a 1615.00 6497.00 479 y252 a 1745.00 728.50 549 y182 a 1745.00 3633.50 619 y112 a 1745.00 6538.50 480 y251 a 1615.00 770.00 550 y181 a 1615.00 3675.00 620 y111 a 1615.00 6580.00 481 y250 a 1745.00 811.50 551 y180 a 1745.00 3716.50 621 y110 a 1745.00 6621.50 482 y249 a 1615.00 853.00 552 y179 a 1615.00 3758.00 622 y109 a 1615.00 6663.00 483 y248 a 1745.00 894.50 553 y178 a 1745.00 3799.50 623 y108 a 1745.00 6704.50 484 y247 a 1615.00 936.00 554 y177 a 1615.00 3841.00 624 y107 a 1615.00 6746.00 485 y246 a 1745.00 977.50 555 y176 a 1745.00 3882.50 625 y106 a 1745.00 6787.50 486 y245 a 1615.00 1019.00 556 y175 a 1615.00 3924.00 626 y105 a 1615.00 6829.00 487 y244 a 1745.00 1060.50 557 y174 a 1745.00 3965.50 627 y104 a 1745.00 6870.50 488 y243 a 1615.00 1102.00 558 y173 a 1615.00 4007.00 628 y103 a 1615.00 6912.00 489 y242 a 1745.00 1143.50 559 y172 a 1745.00 4048.50 629 y102 a 1745.00 6953.50 490 y241 a 1615 . 00 1185 . 00 560 y171 a 1615 . 00 4090 . 00 630 y101 a 1615 . 00 6995 . 00 pad layout [
data sheet s15817ej2v0ds 7 pd161623 table 2?1. pad layout (4/4) pad pad name pad pad pad name pad no. type x y no. type x y 631 y100 a 1745.00 7036.50 701 y30 a 1745.00 9941.50 632 y99 a 1615.00 7078.00 702 y29 a 1615.00 9983.00 633 y98 a 1745.00 7119.50 703 y28 a 1745.00 10024.50 634 y97 a 1615.00 7161.00 704 y27 a 1615.00 10066.00 635 y96 a 1745.00 7202.50 705 y26 a 1745.00 10107.50 636 y95 a 1615.00 7244.00 706 y25 a 1615.00 10149.00 637 y94 a 1745.00 7285.50 707 y24 a 1745.00 10190.50 638 y93 a 1615.00 7327.00 708 y23 a 1615.00 10232.00 639 y92 a 1745.00 7368.50 709 y22 a 1745.00 10273.50 640 y91 a 1615.00 7410.00 710 y21 a 1615.00 10315.00 641 y90 a 1745.00 7451.50 711 y20 a 1745.00 10356.50 642 y89 a 1615.00 7493.00 712 y19 a 1615.00 10398.00 643 y88 a 1745.00 7534.50 713 y18 a 1745.00 10439.50 644 y87 a 1615.00 7576.00 714 y17 a 1615.00 10481.00 645 y86 a 1745.00 7617.50 715 y16 a 1745.00 10522.50 646 y85 a 1615.00 7659.00 716 y15 a 1615.00 10564.00 647 y84 a 1745.00 7700.50 717 y14 a 1745.00 10605.50 648 y83 a 1615.00 7742.00 718 y13 a 1615.00 10647.00 649 y82 a 1745.00 7783.50 719 y12 a 1745.00 10688.50 650 y81 a 1615.00 7825.00 720 y11 a 1615.00 10730.00 651 y80 a 1745.00 7866.50 721 y10 a 1745.00 10771.50 652 y79 a 1615.00 7908.00 722 y9 a 1615.00 10813.00 653 y78 a 1745.00 7949.50 723 y8 a 1745.00 10854.50 654 y77 a 1615.00 7991.00 724 y7 a 1615.00 10896.00 655 y76 a 1745.00 8032.50 725 y6 a 1745.00 10937.50 656 y75 a 1615.00 8074.00 726 y5 a 1615.00 10979.00 657 y74 a 1745.00 8115.50 727 y4 a 1745.00 11020.50 658 y73 a 1615.00 8157.00 728 y3 a 1615.00 11062.00 659 y72 a 1745.00 8198.50 729 y2 a 1745.00 11103.50 660 y71 a 1615.00 8240.00 730 y1 a 1615.00 11145.00 661 y70 a 1745.00 8281.50 731 dummy a 1745.00 11206.50 662 y69 a 1615.00 8323.00 732 dummy a 1745.00 11257.50 663 y68 a 1745.00 8364.50 733 dummy a 1745.00 11307.50 664 y67 a 1615.00 8406.00 734 dummy b 1340.00 11374.00 665 y66 a 1745.00 8447.50 735 dummy b 440.00 11374.00 666 y65 a 1615.00 8489.00 736 dummy b -460.00 11374.00 667 y64 a 1745 . 00 8530 . 50 737 dummy b - 1360 . 00 11374 . 00 668 y63 a 1615.00 8572.00 669 y62 a 1745.00 8613.50 670 y61 a 1615.00 8655.00 671 y60 a 1745.00 8696.50 672 y59 a 1615.00 8738.00 673 y58 a 1745.00 8779.50 674 y57 a 1615.00 8821.00 675 y56 a 1745.00 8862.50 676 y55 a 1615.00 8904.00 677 y54 a 1745.00 8945.50 678 y53 a 1615.00 8987.00 679 y52 a 1745.00 9028.50 680 y51 a 1615.00 9070.00 681 y50 a 1745.00 9111.50 682 y49 a 1615.00 9153.00 683 y48 a 1745.00 9194.50 684 y47 a 1615.00 9236.00 685 y46 a 1745.00 9277.50 686 y45 a 1615.00 9319.00 687 y44 a 1745.00 9360.50 688 y43 a 1615.00 9402.00 689 y42 a 1745.00 9443.50 690 y41 a 1615.00 9485.00 691 y40 a 1745.00 9526.50 692 y39 a 1615.00 9568.00 693 y38 a 1745.00 9609.50 694 y37 a 1615.00 9651.00 695 y36 a 1745.00 9692.50 696 y35 a 1615.00 9734.00 697 y34 a 1745.00 9775.50 698 y33 a 1615.00 9817.00 699 y32 a 1745.00 9858.50 700 y31 a 1615 . 00 9900 . 00 pad layout [
data sheet s15817ej2v0ds 8 pd161623 3. pin functions 3.1 power supply system pins symbol pin name pad no. i/o function v dd1 logic power supply 77, 95 ? power supply pin for logic circuit v dd2 i/o power supply 96, 108, 109 ? power supply pin for i/o buffer v s driver power supply 103, 104 ? power supply pin for driver circuit v ss ground 94, 97, 98, 105 ? ground pin for logic and driver circuits v 0 to v 5 v rh v rl1 , v rl2 power supply for -curve correction 120 to 125, 119, 126, 127 ? the pd161623 includes power supplies and registers for the -curve, so if the characteristics of the -curve and lcd panel in the pd161623 match, leave v 0 to v 5 , v rh , v rl1 , v rl2 open. if some kind of correction is required, adjust the -curve by connecting registers between the v 0 to v 5 , v rh , v rl1 , v rl2 pins (see 5.9 -curve correction power supply circuit ). v dd1 (mode) mode setting pull-up power supply 81, 85 ? pull-up power supply pin for mode setting v dd2 (mode) mode setting pull-down power supply 42, 116 ? pull-down power supply pin for mode setting v ss (mode) mode setting ground 35, 44, 46, 48, 68, 74, 79, 83, 113, 118, 128, 140 ? ground pin for mode setting 3.2 logic system pins (1/2) symbol pin name pad no. i/o function this pin is used to select the cpu interface mode. psx 0 cpu interface mode h 18-bit parallel interface l 16-bit parallel interface psx 0 cpu interface selection 80 input /cs chip select 69 input this pin is used for chip select signals. when /cs = l, the chip is active and can perform data input/output operations including command and data i/o. /reset reset 70 input when /reset is l, an internal reset is performed. the reset operation is executed at the /reset signal level. be sure to perform reset via this pin at power application. /rd (e) read (enable) 73 input when i80 series parallel data transfer (/rd) has been selected, the signal at this pin is used to enable read operations. data is output to the data bus only when this pin is low. when m68 series parallel data transfer (e) has been selected, the signal at this pin is used to enable read/write operations. /wr (r, /w) write (read/write) 72 input when i80 series parallel data transfer (/wr) has been selected, the signal at this pin is used to enable write operations. data is written at the rising edge of this signal. when m68 series parallel data transfer (r, /w) and serial data has been selected, this pin is used to determine the direction of data transfer. l: write h: read c86 select interface 82 input this pin is used to switch between interface modes (i80 series cpu or m68 series cpu). l: selects i80 series cpu mode h: selects m68 series cpu mode
data sheet s15817ej2v0ds 9 pd161623 (2/2) symbol pin name pad no. i/o function d 0 to d 17 data bus 67 to 50 i/o these pins comprise 18-bit bi-directional data. when the chip is not selected, d 0 to d 17 are in high impedance mode. rs data/command selection 71 input when parallel data transfer has been selected, this pin is usually connected to the least significant bit of the standard cpu address bus and is used to distinguish between data from display data and commands. rs = h: indicates that data from d 0 to d 17 is display data. rs = l: indicates that data from d 0 to d 17 is commands. dtx data major select 84 input when parallel data transfer has been selected, this pin is selected data major selection that inputs display data through serial interface. dtx = h: 1-pixel/18-bit mode dtx = l: 1-pixel/16-bit mode osc sel oscillation signal selection 43 input this pin is for oscillation signal selection. when is used external resistance connected oscillation circuit, this pin sets h. when in used cr internal oscillation circuit, this pin sets l. osc sel = h: external resistance connected oscillation circuit select osc sel = l: cr internal oscillation circuit select osc in oscillation signal 47 input this pin is for oscillation signal input. osc sel = h: connect 42 k ? resistance between osc in and osc out . (240 line, in case of ngo = 0) osc sel = l: leave it open. osc out oscillation signal 45 output this pin is for oscillation signal input. osc sel = h: connect 42 k ? resistance between osc in and osc out . (240 line, in case of ngo = 0) osc sel = l: leave it open. cstb gstb logic signal 49 output this pin outputs stb signal for gate driver leveled by interface power supply voltage (v dd1 ). this output signal is reverse signal of gstb. op 0 to op 7 output port 141 to 148 output this is a general-purpose output port. the status of these pins (h or l) can be write via a command. leave open when in unused. 3.3 gate driver ic control pins symbol pin name pad no. i/o function goe 1 oe 1 output for gate driver 151 output this pin is an output pin for the low power mode (for the oe 1 ). connect to the oe 1 pin of the gate driver. timing signal for output, refer to 5.4 display timing generator. goe 2 oe 2 output for gate driver 152 output this pin is the oe 2 output for the gate driver. connect to the oe 2 pin of the gate driver. timing signal for output, refer to 5.4 display timing generator. gstb stb output for gate driver 149 output this pin is the stb output for the gate driver. connect to the stvr or stvl pin of the gate driver. timing signal for output, refer to 5.4 display timing generator. gclk clk output for gate driver 150 output this pin is the clk output for the gate driver. connect to the clk pin of the gate driver.
data sheet s15817ej2v0ds 10 pd161623 3.4 power supply control pins symbol pin name pad no. i/o function lpmp low power mode signal 90 output low power mode control signal output pin (for power supply ic). this pin connects to lpm pin of power supply ic. dcon dc/dc converter control 92 output dc/dc converter on/off signal pin for power supply ic. this pin connects dcon pin of power supply ic. rgonp regulator control 91 output regulator on/off control signal pin for power supply ic. this pin connects to rgonp pin of power supply ic. v cd11 , v cd12 v dd1 booster selection 89, 88 output control signal to select x4/x5/x6/x7 booster of power supply ic for v dd1 . connect to the v cd11 and v cd12 pins of the power supply ic. v cd2 v dd2 booster selection 87 output control signal to select x2/x3 booster of power supply ic for v dd2 . connect to the v cd2 pin of the power supply ic. v ce v o level selection 86 output signal for selecting the level of the power supply ic booster voltage, to be used for the maximum voltage of v o . selects that the booster voltage level is either the same level as v dd1 or a multiple of minus 1. connect to the v ce pin of the power supply ic. 3.5 driver-related pins (1/2) symbol pin name pad no. i/o function y 1 to y 528 source output 730 to 468, 457 to 193 output these pins are source output pins. vcom com adjustment 110 output this pin is the common adjustment output pin. vcout1 center rectangle signal output 106, 107 output this pin is the center rectangle signal output (v p-p ) for common modulation between 0 v and v s . vcout2 center rectangle signal output 93 output this pin is the center rectangle signal output (v p-p ) for common modulation between 0 v and v dd2 . bgrin external-power supply connect 115 input this is an external-power supply input pin for vcom. this pin is valid when bgrs (power supply control register 1: r25) = 1. in this case, the reference voltage of the amplifier for setting the common waveform center value is input from outside the pd161623. when bgrs = 0, the pd161623 internal voltage is set as the reference voltage of the amplifier for setting the common waveform center value. in this case, leave it open. vcomr vcom setting register connection 114 input this pin connects an external feedback resistor for setting vcom. this pin is valid when fbr sel = l. in this case, connect a feedback resistor between the vcom pin and gnd. when fbr sel = h, the amplifier for setting the common waveform center value operates as a voltage follower. in this case, leave it open.
data sheet s15817ej2v0ds 11 pd161623 (2/2) symbol pin name pad no. i/o function fbr sel vcom setting external circuit select 117 input this pin is used to select the method of adjusting the amplifier for setting the common waveform center value used to set the common drive waveform center level. fbr sel = h: voltage follower circuit used (vcomr connected to vcom internally) fbr sel = l: external feedback resistor used cvph, cvpl, cvnh, cvnl basis power supply pin for -corrected power supplies 102, 101, 100, 99 output this is operational amplifier output pin for the g-corrected power supplies. normally, this pin connects capacitor of 1.0 f. dac 0 to dac 7 d/a converter value setting 139 to 132 input these pins set the reference voltage of the amplifier for setting the vcom value used to set the common drive waveform center level. these pins are valid when the vcom output center value setting register (r29) = 00h and bgrs (r25: d 6 ) = 0. for more details, refer to 5.5 common adjustment circuit. remark t.b.d. (to be determined.) 3.6 test or other pins symbol pin name pad no. i/o function tout 0 to tout 17 , tosco source output 34 to 17, 41 output this is output pin when pd161623 is in test mode. normally, leave it open. tstrtst, tstvihl, tosci, toscseli, toscselo, tbsel1, tbsel2, psx 1 com adjustment 37, 36, 40, 39, 38, 129, 130, 78 output these pins are to set up test mode of pd161623. normally, fixed it to v ss . si, scl test input 75, 76 input these pins are to set up test mode of pd161623. normally, fixed it to either v dd1 or v ss . tbgr test input/output 131 i/o this is output pin when pd161623 is in test mode. normally, leave it open. dummy dummy 1 to 16, 111, 112, 153 to 192, 458 to 467, 731 to 737 ? dummy pin
data sheet s15817ej2v0ds 12 pd161623 4. pin i/o circuits and recommended connection of unused pins the i/o circuit types of each pin and recommended connection of unused pins are described below. pin name input type i/o power supply recommended connection of unused pins note psx 0 schmitt trigger input v dd1 mode setting pin 1 /reset schmitt trigger input v dd1 always reset on power application ? /rd(e) schmitt trigger input v dd1 connect to v dd1 (when i80 series interface) ? c86 schmitt trigger input v dd1 mode setting pin 1 d 0 to d 17 schmitt trigger i/o v dd1 ?? rs schmitt trigger input v dd1 register setting pin 2 op 0 to op 7 ? output v dd2 leave open ? osc in cmos input v dd2 input external clock (in osc sel = h mode) ? osc out cmos input v dd2 leave open (in osc sel = h mode) ? cstb ? output v dd1 leave open ? osc sel schmitt trigger input v dd2 mode setting pin 3 goe 1 ? output v dd2 always connect to the gate driver ? goe 2 ? output v dd2 always connect to the gate driver ? gstb ? output v dd2 always connect to the gate driver ? gclk ? output v dd2 always connect to the gate driver ? lpmp ? output v dd2 leave open ? dcon ? output v dd2 always connect to the power ic ? rgonp ? output v dd2 always connect to the power ic ? v cd11 , v cd12 ? output v dd2 always connect to the power ic ? v cd2 ? output v dd2 always connect to the power ic ? v ce ? output v dd2 always connect to the power ic ? v com ? output v s leave open (frb sel = h) ? vcout1 ? output v s leave open ? vcout2 ? output v dd2 leave open ? bgrin ? input v s leave open (bgrs = 0 [r25]) ? vcomr ? input v s leave open (frb sel = h) ? tout 0 to tout 17 ? output v dd2 leave open ? tosco ? output v dd2 leave open ? tstrtst ? input v dd2 connect to v ss ? tstvihl ? input v dd2 connect to v ss ? tosci ? input v dd2 connect to v ss ? toscseli ? input v dd2 connect to v ss ? toscselo ? input v dd2 connect to v ss ? tbsel1 ? input v dd2 connect to v ss ? tbsel2 ? input v dd2 connect to v ss ? tbgr ? input v dd2 connect to v ss ? psx 1 ? input v dd1 connect to v ss ? scl ? input v dd1 connect to v dd1 or v ss ? si ? input v dd1 connect to v dd1 or v ss ? dtx schmitt trigger input v dd1 connect to v dd1 or v ss 1 fbr sel cmos input v dd2 connect to v dd2 or v ss 3 notes 1. connect to v dd1 or v ss , depending on the mode selected. 2. input either h or l by cpu, depending on the register selected. 3. connect to v dd2 or v ss , depending on the mode selected.
data sheet s15817ej2v0ds 13 pd161623 5. description of functions 5.1 cpu interface 5.1.1 selection of interface type the pd161623 chip transfers data using a 18-bit bi-directional data bus (d 17 to d 0 ), 16-bit bi-directional data bus (d 15 to d 0 ). setting the polarity of the psx 0 pin as either h or l enables the selections shown in table 5?1 below. table 5 ? 1. psx 0 mode /cs rs /rd (e) /wr (r, /w) c86 d 17 , d 16 d 15 to d 8 d 7 to d 0 h 18-bit parallel /cs rs /rd (e) /wr (r, /w) c86 d 17 , d 16 d 15 to d 8 d 7 to d 0 l 16-bit parallel /cs rs /rd (e) /wr (r, /w) c86 hi-z note d 15 to d 8 d 7 to d 0 note hi-z: high impedance 5.1.2 selection of data transfer mode in the pd161623, when the 16-bit parallel interface is selected, there are two types of modes to transfer data to display ram. the mode can be selected as follows with the dtx command. when using the 16-bit parallel interface and the 1-pixel/18-bit mode (dtx = h) is selected, one pixel of display data must be transferred every two words, as shown in figure 5 ? 4. at this time, the data of db 15 to db 9 is treated as invalid data. when the 1-pixle/16-bit mode (dtx = l) is selected, one pixel of display data is transferred every word. however, because one pixel data is 16 bits long, the display color range is restricted to 65,536. when the 18-bit parallel interface is used, the data transfer method is fixed to 1-pixel/18-bit mode, regardless of the setting of the dtx pin. because the display ram in the pd161623 has a 1-pixel/18-bit configuration, when using the 1-pixel/16-bit mode (dtx = l), it will be necessary to add supplementary data for the two-bit data deficiency that occurs when (16-bit) data is transferred from the cpu. for the relationship between the display data and the supplementary data set by the data supplement register, refer to figure 5 ? 3. table 5 ? 2. psx 0 interface mode dtx mode h 18-bit parallel x note 1-pixel/18-bit h 1-pixel/18-bit l 16-bit parallel l 1-pixel/16-bit note x: don?t care (h or l)
data sheet s15817ej2v0ds 14 pd161623 table 5 ? 3. data supplement register supplemented display data cd12 when 1-pixel/16-bit mode is used, the value set by this flag is stored in the display ram as d 12 data. cd0 when 1-pixel/16-bit mode is used, the value set by this flag is stored in the display ram as d 0 data. figure 5 ? ? ? ? 1. relationship between data bus and display ram data (18-bit parallel interface) db 18-bit data dot 1 dot 2 dot 3 data bus side display ram side 1st pixel 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 0 db 1 d 12 d 13 d 14 d 15 d 16 d 17 figure 5 ? ? ? ? 2. relationship between data bus and display ram data (1-pixel/18-bit mode [dtx = h], 16-bit parallel interface) 9-bit data (2nd word) dot 1 dot 2 dot 3 data bus side display ram side 1st pixel db 8 db 7 db 6 db 5 db 4 db 3 db 2 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 0 db 1 d 12 d 13 d 14 d 15 d 16 d 17 9-bit data (1st word) db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 0 db 1 note when in used 16-bit parallel interface, db 15 to db 9 is treated as invalid data. figure 5 ? ? ? ? 3. relationship between data bus and display ram data (1-pixel/16-bit mode [dtx = l], 16-bit parallel interface) data supplement function dot 1 dot 2 dot 3 display ram side 1st pixel cd 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cd 0 d 12 d 13 d 14 d 15 d 16 d 17 note note 16-bit data data bus side db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 0 db 1 note when in used 16-bit parallel interface, display ram data d 12 and d 0 are added to the 16-bit data by the data supplement register (r4), and written to the display ram as 18-bit data.
data sheet s15817ej2v0ds 15 pd161623 figure 5 ? ? ? ? 4. 16-bit parallel interface date transfer (1-pixel/18-bit mode [dtx = h]) /cs /wr d 15 1-pixel data invalid 2nd word 1st word rs d 14 d 13 d 9 d 8 d 7 d 6 d 1 d 0 invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid d 8 d 7 d 6 d 17 d 16 d 15 d 8 d 7 d 6 d 17 d 16 d 15 d 1 d 0 d 10 d 9 d 1 d 0 d 10 d 9 1-pixel data 2nd word 1st word
data sheet s15817ej2v0ds 16 pd161623 5.1.3 parallel interface when the parallel interface has been selected, setting the c86 pin as either h or l enables a direct connection to an i80 series or m68 series cpu (see table 5?4 below). table 5 ? 4. c86 mode /rd (e) /wr (r, /w) psx 0 d 17 , d 16 d 15 to d 8 d 7 to d 0 hd 17 , d 16 d 15 to d 8 d 7 to d 0 h m68 series cpu er, /w l hi-z note d 15 to d 8 d 7 to d 0 hd 17 , d 16 d 15 to d 8 d 7 to d 0 l i80 series cpu /rd /wr l hi-z note d 15 to d 8 d 7 to d 0 note hi-z: high impedance. leave it open. the data bus signal is identified according to the combination of the rs, /rd (e), and /wr (r, /w) signals, as shown in the following table 5?5. table 5 ? 5. common m68 series cpu i80 series cpu rs r, /w /rd /wr function h h l h read display data h l h l write display data l h l h prohibited l l h l write to control index register
data sheet s15817ej2v0ds 17 pd161623 (1) i80 series parallel interface when i80 series parallel data transfer has been selected, data is written to the pd161623 at l period of the /wr signal. the data is output to the data bus when the /rd signal is l. figure 5?5. i80 series interface data bus status /cs /wr /rd dbn hi-z hi-z data write data read valid data (2) m68 series parallel interface when m68 series parallel data transfer has been selected, data is written at the h period of the e signal when the r,/w signal is l. in a data read operation, data is output at the rising edge of the e signal in a period when the r,/w signal is h. the data bus is released (hi-z) at the falling edge of the e signal. figure 5?6. m68 series interface data bus status (when data read) /cs r,/w e dbn hi-z hi-z valid data hi-z
data sheet s15817ej2v0ds 18 pd161623 5.1.4 chip select the pd161623 has two chip select pins (/cs). the cpu parallel interface can be used only when /cs = l. when the chip select pin is inactive, d 0 to d 17 are set to high impedance (invalid) and input of rs, /rd, or /wr is not active. 5.1.5 access to display data ram and internal registers when the cpu accessed the pd161623, the cpu only has to satisfy the requirement of the cycle time (t cyc ) and can transfer data at high speeds. usually, it is not necessary for the cpu to take wait time into consideration. a high-speed ram write function, as well as the ordinary ram write function, is provided for writing data to the display data ram. by using the high-speed write function, data can be written to the display ram at an access speed two times faster than that of the ordinary ram write function. therefore, applications, such as motion picture display where the display data must be rewritten at high speeds, can be supported. for details, refer to 5.2.5 high-speed ram write mode dummy data is not required when writing data. in the pd161623, only for reading display data, needs dummy data. this relationship is shown in figure 5?7. note that when in write mode of data at high speed for data read mode of read cycle time, this mode equals to normal mode.
data sheet s15817ej2v0ds 19 pd161623 figure 5 ? 7. image of internal access to display ram writing /wr data n n+1 n+2 n+3 bus holder write signal n n+1 n+2 n+3 reading /wr /rd data n n n n+1 bus holder column address preset n increment n+1 n+2 nn n+1 n+2 read signal address preset address set #n dummy read data read #n data read #n
data sheet s15817ej2v0ds 20 pd161623 5.2 display data ram this ram stores dot data for display and consists of 3,168 bits (176 x 18) x 240 bits. any address of this ram can be accessed by specifying an x address and an y address. display data d 0 to d 17 transmitted from the cpu corresponds to the pixels on the lcd (refer to table 5 ? 8). figure 5 ? ? ? ? 8. display data ram d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 dot 1 dot 2 dot 3 pixel 1 (= 1 x address) pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00h 01h 02h 03h 04h 05h 06h 07h lcd panel 5.2.1 x address circuit an x address of the display data ram is specified by using the x address register (r6) as shown in figure 5 ? 9. the specified x address is incremented by one each time display data is written or read. in the increment mode, the x address is incremented up to afh. if more display data is written or read, the y address is incremented, and the x address returns to 00h. 5.2.2 y address circuit a y address of the display data ram is specified by using the y address register (r7) as shown in figure 5 ? 9. the y address is incremented each by one when one each time display is written or read and x address is incremented to last address. when the y address has been incremented up to efh and the x address up to the final address, if further display data is read or written, the x and y addresses return to 00h.
data sheet s15817ej2v0ds 21 pd161623 5.2.3 column address circuit when the contents of the display data ram are displayed, column addresses are output to the source output pins as shown in figure 5 ? 9. the correspondence relationship between the column addresses of the display ram and source outputs can be reversed by the adc flag (source driver direction select flag) of control register 1 (r0) as shown in table 5 ? 6. this reduces the restrictions on chip layout when the lcd module is assembled. table 5 ? ? ? ? 6. relationship between column address of display ram and source output source output y 1 y 2 y 527 y 528 0 000h 001h column address 20eh 20fh adc 1 20fh 20eh column address 001h 000h figure 5?9. pd161623 ram addressing adc=0 y1 y2 y3 y4 y5 y6 --- --- y523 y524 y525 y526 y527 adc=1 y528 y527 y526 y525 y524 y523 --- --- y6 y5 y4 y3 y2 x-address --- --- column addr e 000h 001h 002h 003h 004h 005h --- --- 20ah 20bh 20ch 20dh 20eh d17--d12 d11--d6 d5---d0 d17--d12 d11--d6 d5---d0 d17--d12 d11--d6 d5---d0 d17--d12 d11--d6 r,/l=h r,/l=l adr=0 adr=1 o1 o240 00h efh o2 o239 01h eeh |||| o87 o90 56h 59h o88 o89 57h 58h o89 o88 58h 57h display area o90 o87 59h 56h |||| o239 o2 eeh 01h o240 o1 efh 00h afh gate out p ut y-address 1st p ixel 2nd p ixel 1st p ixel 2nd p ixel source out p ut 000h 001h aeh scan direction
data sheet s15817ej2v0ds 22 pd161623 5.2.4 arbitrary address area access (window access mode (was)) with the pd161623, any area of the display ram selected by the min.x/y address registers (r8 and r10) and max. ? x/y address registers (r9 and r11) can be accessed. when was of data access control register (r5) is set to 1, the window access mode is then selected and accessed by setting only address area of the min. ? x/y address registers and max.x/y address registers. . the address scanning setting is also valid in this mode, in the same manner as when data is normally written to the display ram. in addition, data can be written from any address by specifying the x address register (r6) and y address register (r7). note that the display ram must be accessed after setting the x address register (r6) and y address register (r7) if the window access area has been set or changed by the min. ? x/y address register or max. ? x/y address register. figure 5 ? ? ? ? 10. example of incrementing address when in window access mode start point end point efh 00h afh 00h min. x address . min. y address . max. y address . max. x address . . . . cautions 1. when using the window access mode, the relationship between the start point and end point shown in the table below must be established. item address relationship x address 00h min. ? x address x address (r6) max. ? x address afh y address 00h min. ? y address y address (r7) max. ? y address efh 2. if invalid address data is set as the min./max. ? ? ? ? address, operation is not guaranteed. 3. do not specify any value other than the address value 2n ? ? ? ? 2 (n = 1 to 88) for the x address in the high-speed ram access mode. the operation is not guaranteed if invalid address data is set. 4. access the display ram after setting the x address register (r6) and y address register (r7) if the window access area has been set or changed by the min. ? ? ? ? x/y address register or max. ? ? ? ? x/y address register.
data sheet s15817ej2v0ds 23 pd161623 figure 5 ? ? ? ? 11. example of sequence in window access mode no data access control register (r5) min. data writing complete? sets start point. ye s (was = 1) sets end point. sets window access mode. . x address register (r8) min. . y address register (r10) max. . x address register (r9) max. . y address register (r11) x address register (r6) y address register (r7) write display data start end
data sheet s15817ej2v0ds 24 pd161623 5.2.5 high-speed ram write mode with the pd161623, two types of access modes can be selected for accessing the display ram. the pd161623 has a high-speed ram write function, as well as an ordinary ram write function. by using the high- speed write function, data can be written to the display ram at an access speed two times faster than that of the ordinary ram write function. therefore, applications, such as motion picture display where the display data must be rewritten at high speeds, can be supported. when the high-speed ram write mode is selected by using bstr of the data access control register (r5), data is temporarily stored in an internal register of the pd161623. when data of 36 bits (18 bits x 2) has been stored in the register, it is written to the display ram. it is also possible to write the next data to the internal register while the first data is being written to the ram. in the high-speed ram write mode, however, the cpu must transmit data in units of 2 pixel data (1-pixel/18-bit mode: 36-bit, 1-pixel/16-bit mode: 32-bit) have been written to the internal register. if data of less than 2-pixel data is transmitted in the high-speed ram write mode, this data is not written to the display ram. therefore, cpu data is not reflected on the lcd display even if it is transmitted. in this case, the data that is not reflected remains stored in the register. when the next data is transmitted, it is written to the register from where the preceding data is stored. however, if the chip select signal is disserted inactive (/cs = h) in the middle of data transfer, and then asserted active again and when the display data write is set, the register is initialized. consequently, the data stored in the register is lost. it is therefore recommended to transmit display data in 2-pixel units when using the high-speed ram write mode. figure 5?12. image of operation in high-speed write mode 36-bit register display ram 36-bit 36-bit 36-bit 36 36 36 36 18 18 18 data supplement function interface circuit display data 18/16 parallel/serial data supplement register (r4) caution do not specify any value other than the address value 2n ? ? ? ? 2 (n = 1 to 88) for the x address (r6) in the high-speed ram access mode. the operation is not guaranteed if invalid address data is set.
data sheet s15817ej2v0ds 25 pd161623 figure 5 ? ? ? ? 13. example of sequence in high-speed ram write mode (with 18-bit parallel interface) no high speed ram write mode setting end of data next processing ye s (r5: bstr[d6] = 1) sets the high-speed ram write mode. x address setting register (r6) note y address setting register (r7) write display data start end 1-pixel (2n ? 1) of display data (18 bit) 2-pixel (2n) of display data (18 bit) data write sequence (writing data in 2-pixel units) n: n 1 note do not specify any value other than the address value 2n ? 2 (n = 1 to 88) for the x address (r6) in the high-speed ram access mode. the operation is not guaranteed if invalid address data is set.
data sheet s15817ej2v0ds 26 pd161623 5.3 oscillator the pd161623 has a cr oscillator (with external r resistance), which generate the display clock. when osc sel is l, an internal cr oscillator is selected. on the other hand, leave both osc in and ocs out pin open. when osc sel is h, an external connection oscillator is selected. connect 42 k ? resistance between osc in an osc out pin (when in used 240 lines). this oscillator also has a calibration function, which is available by itself to set the number of frame frequency of display driving. frame frequency calibration is set by calibration register (r45). the time to select one line is set by the calibration start and stop commands. figure 5?14. frame frequency calibration calibration command register n-bit counter clock internal osc start/stop the calibration function involves counting the number of oscillation clocks generated between the start and stop signals and storing that number in a register. the number of oscillation clocks is then continually compared with this register value in subsequent operations, and the time of the clock number stored in the register is set as 1 line selection time, and used as the internal reference clock. using the time to set calibration (t cal ) can be selected either t cal or t cal x 2 through control register 2 (r1): lts. figure 5?15. calibration function timing (lts [r1] = 0) 1 4 3 2 5 7 6 1 4 3 2 osc1 calibration start calibration stop t cal (1 line time) osc2 t cal = 1/(f frame x n) f frame = frame frequency n: line numbers
data sheet s15817ej2v0ds 27 pd161623 5.4 display timing generator 5.4.1 display timing the pd161623 generates the tft-:cd drive timing inside the pd161623. the tft-lcd panel is driven at the timing of one line selection period generated based on the calibration time (t cal ) set by the calibration function, as shown in the figure below. one line selection period is made up of a pre-charge period, a source output period, and the pd161623 output control clock. the pre-charge and source output periods are set by the pre-charge period setting register (r46) and calibration register (r45), respectively, based on the following expressions. 1 line selection period = t cal pre-charge period = t pr source output period = t sout t cal : calibration setting time [r45] t pr = (1/f osc ) x (clk pr + 2 clk) t sout = t cal - (t pr + 3 clk) clk cal : calibration setting time (t cal ) clock number = t cal (1/f osc ) clkpr: pre-charge peiod setting register clock number [r46: plimn] n 1 clk = 1/f osc f osc : oscillator frequency
data sheet s15817ej2v0ds 28 pd161623 figure 5?16. 1-line select time f osc gclk gstb sn t pr 1 line select time pre-charge time goe 1 vcout gn 1 0 1 1 1234 5 6 78 9 1 0 1 1 1 2 3 45 6 output control basis clock 2 clk 2 clk t cal1 source output time: t sout output switching time (1 clk) 1 clk 4 clk
data sheet s15817ej2v0ds 29 pd161623 the display timing generator generates the timing signals for the internal timing of the source driver and for the gate driver. the output timings for normal operation, for normal operation stand-by mode, and for stand-by mode normal operation, are shown below. figure 5?17. during normal operation (during line inversion) gstb data output line no. 240 dummy 1 2 345 240 dummy 12 gclk goe 1 goe 2 sn vcout g 1 g 2 g 3 g 240
data sheet s15817ej2v0ds 30 pd161623 figure 5?18. normal operation stand-by input (during line inversion) gstb data output line no. 240 dummy 1 2 345 240 dummy gclk goe 1 goe 2 sn vcout g 1 g 2 g 3 g 240 g 4 stand-by statement (2) (1) stand-by mode start stand-by command input
data sheet s15817ej2v0ds 31 pd161623 figure 5?19. normal operation stand-by input (during line inversion) (1) reference f osc gclk gstb 1 line select time (3 line) goe 1 g 3 g 2 1 clk sn 1 line select time (4 line) goe 2 v ss g 4 vcout stand-by mode start stand-by command v ss
data sheet s15817ej2v0ds 32 pd161623 figure 5?20. normal operation stand-by input (during line inversion) (2) reference f osc gclk gstb 1 line select time (dummy line) goe 1 g 3 g 240 sn stand-by time goe 2 v ss g 4 vcout stand-by command v ss 1 clk oscillation stop all gate on
data sheet s15817ej2v0ds 33 pd161623 figure 5?21. stand-by return to normal operation (during line inversion) gstb data output line no. dummy 1 2 34 5 gclk goe 1 goe 2 sn vcout g 1 g 2 g 3 g 240 g 4 stand-by release command input
data sheet s15817ej2v0ds 34 pd161623 5.5 common adjustment circuit to generate common output, the center voltage of the common waveform is output from the vcom pin along with output of a 0 to v s (v) square waveform from the vcout1 pin and 0 to v dd1 (v) from vcout2. the level of the vcom output can be adjusted using as external resistor. figure 5?22. common adjustment circuit vcomr vcout1, vcout2 vcout1: v p-p = v s 0 v v s , v cc1 vcommon waveform center setting vcommon r1 r2 r3 c1 bgrin d/a converter r29 r25 (bgrs) dac 7 vbgr fbr sel dac 0 vcom rectangle waveform value vcout2: v p-p = v cc1 v s r25 (pvcom) the vcom voltage formulas are shown below. com voltage = (1+r1/r2) x vbgr x ( 256) vbgr = 3.0 v typ. : setting of vcom electric volume register (r29) < when internal power supply is used 2 (d 6 of r25: bgrs = 0, d 3 of pvcom = 1) > com voltage = (1+r1/r2) x v s x ( 256) : setting of vcom electric volume register (r29) com voltage = (1+r1/r2) x vbgrin vbgrin = external supply voltage (voltage input from bgrin) use the values listed below as a guideline. the user is responsible for ultimately determining the resistance values and recommended values based on careful evaluation on actual panels. r1: 200 k ? r2: 51 to 100 k ? r3: 51 to 100 k ? c1: 10 f
data sheet s15817ej2v0ds 35 pd161623 5.6 rectangular signal generator this circuit generates a common rectangular signal. a rectangular wave of 0 to v s (v) is output from the vcout1 pin, and a wave of 0 to v dd2 (v) is output from the vcout2 pin. the common output wave necessary for driving an lcd can be generated by connecting an external circuit as shown in figure 5?22. 5.7 reference voltage generator (vbgr) the pd161623 has a reference voltage generator for the voltage regulator. this reference voltage generator generates a constant voltage from v dd2 . the constant voltage generated by this circuit is connected to the input of the operational amplifier that adjusts the center level of the common drive output, via a d/a converter. by using this voltage, therefore, the center level of the common drive output can be kept constant, without being affected by fluctuations in the supply voltage. the common waveform output necessary for driving an lcd can be generated by connecting the external circuit show in figure 5?16. when the internal reference voltage generator is not used (r25: bgrs = 1), directly input the reference voltage to the operational amplifier that adjusts the center level of the common drive output. 5.8 d/a converter circuit the pd161623 is provided with an internal d/a converter to adjust the voltage of the reference voltage generator for the voltage regulator. this d/a converter divides the constant voltage generated by the reference voltage generator (vbfr) by 256, and a level of voltage between vbgr and v ss can be selected by setting the vcom electronic volume register (r29). in addition, this d/a converter also has a function to select a level by using an external pin. if the set value of the vcom electronic volume register (r29) is 00h, the set statuses of the dac 7 to dac 0 pins are valid. table 5?7. setting of vcom electronic volume register (r25: bgrs = 0) ev 7 ev 6 ev 5 ev 4 ev 3 ev 2 ev 1 ev 0 dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 remark dac n set value r29 00h00000000 0dac n 01h00000001 2 02h00000010 3 03h00000011 4 feh11111110 255 ffh11111111 256
data sheet s15817ej2v0ds 36 pd161623 5.9 -curve correction power supply circuit the pd161623 includes a -curve correction power supply circuit. if the internal -curve correction matches the lcd characteristics, no external components are necessary. this power circuit has white level and black level reference voltage generators on the positive and negative polarity sides, and also supports unbalanced driving. the reference voltage generators consist of a d/a converter and an operational amplifier and divide v s to v ss by 256. one level of voltage can be selected by using the -contrast value setting register1 to 4 (r36 to r39) figure 5?23. -curve correction circuit d/a (r37) d/a (r36) d/a (r39) d/a (r38) vph vnh vpl vnl v s v ss sph1 snl1 snh1 spl1 custom sph2 snl2 v ss vrh v 0 v 5 vrl1 spl2 snh2 v s vrl2
data sheet s15817ej2v0ds 37 pd161623 figure 5?24. relationship of tft drive voltage (normally white) vph vnh vpl vnl v s v ss positive polarity negative polarity white black drive level setting register vph positive polarity, black contrast value setting register 1 r36 vnh negative polarity, white contrast value setting register 2 r37 vpl positive polarity, black contrast value setting register 3 r38 vnl negative polarity, white contrast value setting register 4 r39 the value of each amplifier output can be expressed as follows and the value of can be set as shown in table 5?8 and 5 ? 9 by using the contrast value registers (r36, r37, r38, and r39) vnl, vpl, vnh, vph = ( 256) x v s caution the usable range in which each output level of vph, vnh, vpl, and vnl can be set depends on the -curve. table 5?8. -contrast value setting and electronic volume register setting 1 (vph, vnl) r36 gph7gph6gph5gph4gph3gph2gph1gph0 r37 gnh7 gnh6 gnh5 gnh4 gnh3 gnh2 gnh1 gnh0 value setting or status setting 00h00000000fixed to v s (amplifier off) 01h00000001 255 02h00000010 254 03h00000011 253 feh11111110 2 ffh11111111 1
data sheet s15817ej2v0ds 38 pd161623 table 5?9. -contrast value setting and electronic volume register setting 2 (vpl, vnl) r36 gpl7 gpl6 gpl5 gpl4 gpl3 gpl2 gpl1 gpl0 r37 gnl7 gnl6 gnl5 gnl4 gnl3 gnl2 gnl1 gnl0 value setting or statement setting 00h00000000fixed to v s (amplifier off) 01h00000001 1 02h00000010 2 03h00000011 3 feh11111110 254 ffh11111111 255 the relationship between the setting of the contrast value setting register and the driven waveform is explained next, taking the -curve in figure 5?23 as an example. table 5?10. switch status when -curve correction power supply circuit is not used (r36, r37, r38, r39 = 00h) switch status polarity sph1 snl1 snh1 spl1 sph2 snl2 snh2 spl2 positive x x x x on off off on negative x x x x off on on off remark x: switch is normally off with the amplifier off. relationship of drive voltage (normally white) vph vnh vpl vnl v s v ss positive polarity negative polarity white black
data sheet s15817ej2v0ds 39 pd161623 table 5?11. switch status when -curve correction power circuit is used (r36, r37, r38, r39 = other than 00h) switch status polarity sph1 snl1 snh1 spl1 sph2 snl2 snh2 spl2 positive on off off on x x x x negative off on on off x x x x remark x: switch is normally off relationship of drive voltage (normally white) vph vnh vpl vnl v s v ss positive polarity negative polarity white black
data sheet s15817ej2v0ds 40 pd161623 figure 5?25. tft drive voltage level d/a (r37) d/a (r36) d/a (r39) d/a (r38) vph vnh vpl vnl v s v ss sph1 snl1 snh1 spl1 sph2 snl2 v ss vrh v 0 v 5 vrl1 spl2 snh2 v s vrl2 drive voltage range
data sheet s15817ej2v0ds 41 pd161623 table 5?12. -curve correction circuit ( -correction resistance) glay scale dn+5 dn+4 dn+3 dn+2 dn+1 dn r 1 1.587 positive voltage negative voltage 0 000000 r2 1.226 4.901 0.107 1 000001 r3 2.453 4.824 0.190 2 000010 r4 3.390 4.671 0.356 3 000011 r5 4.112 4.459 0.586 4 000100 r6 4.905 4.202 0.864 5 000101 r7 1.731 3.895 1.196 6 000110 r8 1.443 3.787 1.313 7 000111 r9 1.587 3.697 1.411 8 001000 r10 1.515 3.598 1.519 9 001001 r11 1.082 3.503 1.621 10 001010 r12 1.082 3.436 1.694 11 001011 r13 1.154 3.368 1.768 12 001100 r14 1.226 3.296 1.846 13 001101 r15 1.298 3.219 1.929 14 001110 r16 1.082 3.138 2.017 15 001111 r17 0.649 3.070 2.090 16 010000 r18 0.721 3.030 2.134 17 010001 r19 0.794 2.985 2.183 18 010010 r20 0.721 2.935 2.236 19 010011 r21 0.794 2.890 2.285 20 010100 r22 0.505 2.840 2.339 21 010101 r23 0.577 2.809 2.373 22 010110 r24 0.577 2.773 2.412 23 010111 r25 0.577 2.737 2.451 24 011000 r26 0.505 2.701 2.490 25 011001 r27 0.433 2.669 2.524 26 011010 r28 0.433 2.642 2.554 27 011011 r29 0.433 2.615 2.583 28 011100 r30 0.433 2.588 2.612 29 011101 r31 0.505 2.561 2.642 30 011110 r32 0.361 2.529 2.676 31 011111 r33 0.433 2.507 2.700 32 100000 r34 0.433 2.480 2.729 33 100001 r35 0.433 2.453 2.759 34 100010 r36 0.433 2.426 2.788 35 100011 r37 0.433 2.399 2.817 36 100100 r38 0.433 2.372 2.847 37 100101 r39 0.505 2.344 2.876 38 100110 r40 0.433 2.313 2.910 39 100111 r41 0.433 2.286 2.939 40 101000 r42 0.433 2.259 2.969 41 101001 r43 0.505 2.232 2.998 42 101010 r44 0.361 2.200 3.032 43 101011 r45 0.433 2.178 3.057 44 101100 r46 0.433 2.151 3.086 45 101101 r47 0.361 2.124 3.115 46 101110 r48 0.361 2.101 3.140 47 101111 r49 0.361 2.078 3.164 48 110000 r50 0.361 2.056 3.188 49 110001 r51 0.433 2.033 3.213 50 110010 r52 0.433 2.006 3.242 51 110011 r53 0.433 1.979 3.271 52 110100 r54 0.505 1.952 3.301 53 110101 r55 0.505 1.921 3.335 54 110110 r56 0.505 1.889 3.369 55 110111 r57 0.721 1.858 3.403 56 111000 r58 0.721 1.812 3.452 57 111001 r59 0.866 1.767 3.501 58 111010 r60 0.866 1.713 3.560 59 111011 r61 1.587 1.659 3.618 60 111100 r62 2.597 1.560 3.726 61 111101 r63 2.597 1.398 3.901 62 111110 r64 12.047 1.235 4.077 63 111111 r65 7.719 0.482 4.893 total 80.000 dis p la y data resistance (k ? ) out p ut volta g e ( v )
data sheet s15817ej2v0ds 42 pd161623 5.10 partial display mode the pd161623 is provided with a function that allows sections within the screen to be displayed separately (partial display mode). the start line of the area to be displayed in partial display mode is set using the partial display area start line register (r20, r21), the number of lines in the area to be displayed is set using the partial display area line count register (r22, r23), and the color of the area not to be displayed is set using the partial off area color register (r19). if ?1? is set in the partial display area line count registers (r22, r23), the partial display areas each become 1 line. if ?0? is set, there are no partial display areas but only normal display areas. the non-display area indicated by r20 and r22 is called partial 1, and the non-display area indicates by r21 and r23 is called partial 2. the partial 2 setting is enabled only when the partial 1 setting has been performed (when r22 0). therefore, to set only one area as a non-display area, perform only the setting for partial 1. low power consumption cannot be achieved if only the partial mode is set. if low power consumption is required, the mode must be switched to the 8-color mode. figure 5?26. partial display mode 00h 01h 02h 03h adh aeh afh partial display area line number(r22, r23) section not displayed ... display start line (00h) partial display start line (r20, r21) cautions 1. the "scroll step count register (r17)" command is ignored in the partial display mode. 2. the specified partial areas must not directly overlap, and the partial 1 area and partial 2 area must be separated by at least one line. if the areas overlap, only the partial 1 settings are valid, and partial display is not performed for the partial 2 area. 3. when setting the partial display areas, be sure to observe the following relationship. ?00h? r20 (r21) r22 (r23) ?afh? the following sequence is recommended to avoid display malfunction when switching from normal display mode to partial display mode and vice versa.
data sheet s15817ej2v0ds 43 pd161623 (1) recommended sequence for switching from normal display mode to partial display mode disp1 = 1 r0 d 7 <1> display off d 2 pgdn setting r19 <2> partial off area color register setting note1 d 0 display data overwrite <3> display data overwrite note1 (for partial display) d 7 p1sln, p2sln setting r20, <4> partial display area start line setting note1 r21 d 0 d 7 p1awn, p2awn setting r22, <5> partial display area line count setting note1 r23 d 0 dty = 1, color = 1 r0 d 4 , d 2 <6> partial display mode, 8-color mode note2 disp1 = 0 r0 d 7 <7> display on notes 1. <2> to <5> can be executed in any order. 2. <6> must be executed after <4> and <5> have been set.
data sheet s15817ej2v0ds 44 pd161623 (2) recommended sequence for switching from partial display mode to normal display mode disp1 = 1 r0 d 7 <1> display off display data overwrite <2> display data overwrite note (for normal display) dty = 0, color = 0 r0 d 4 , d 2 <3> partial display mode, 260,000-color mode note disp1 = 0 r0 d 7 <4> display on note <2> to <3> can be executed in any order. (3) recommended sequence for switching from partial display mode to partial display mode (switching the partial display area) disp1 = 1 r0 d 7 <1> display off (display data overwrite) <2> display data overwrite notes note1, 2 d 7 p1sln, p2sln setting r20, <3> partial display area start line setting note1 r21 d 0 d 7 p1awn, p2awn setting r22, <4> partial display area line count setting note1 r23 d 0 dty = 1 r0 d 4 <5> partial display mode note3 disp1 = 0 r0 d 7 <6> display on notes 1. <2> to <4> can be executed in any order. 2. execute <2> only when necessary. 3. <5> must be executed after <3> and <4> have been set.
data sheet s15817ej2v0ds 45 pd161623 (4) partial display setting examples setting a-1 register setting value details of setting value partial display area start line register (r20, r21) 00h sets y address 00h partial display area line count register (r22, r23) 78h sets an area of 120 lines setting a-2 register setting value details of setting value partial display area start line register (r20, r21) 78h sets y address 78h partial display area line count register (r22, r23) 78h sets an area of 120 lines setting a-3 register setting value details of setting value partial display area start line register (r20, r21) b4h sets y address b4h partial display area line count register (r22, r23) 78h sets an area of 120 lines setting a-4 register setting value details of setting value partial display area start line register (r20, r21) 3ch sets y address 3ch partial display area line count register (r22, r23) 78h sets an area of 120 lines
data sheet s15817ej2v0ds 46 pd161623 figure 5?27. partial display setting examples partial display area partial display area partial display area partial display area partial display area setting a- 1 gate source 1 1 120 121 240 176 area not displayed setting a- 2 gate source 1 1 120 121 240 176 setting a- 3 gate source 1 1 240 181 180 61 60 181 180 61 60 176 setting a- 4 gate source 1 1 240 176 area not displayed area not displayed area not displayed area not displayed
data sheet s15817ej2v0ds 47 pd161623 5.11 screen scroll the pd161623 has a screen scroll function. any area of the screen can be scrolled by using the scroll area start line register (r15), scroll area line count register (r16), and scroll step count register (r17) to set the y address of the top line of the area to be scrolled, the count of lines of the area to be scrolled, and the scroll step number, respectively. note that in partial mode, the screen scroll function is disabled. table 5?13. scroll area start line register (r15) ssl7 ssl6 ssl5 ssl4 ssl3 ssl2 ssl1 ssl0 start line y address 00000000 00h 00000001 01h 00000010 02h 00000011 03h 10101101 edh 10101110 eeh 10101111 efh table 5?14. scroll area line count register (r16) saw7 saw6 saw5 saw4 saw3 saw2 saw1 saw0 scroll area line number 00000000 1 00000001 2 00000010 3 00000011 4 10101101 238 10101110 239 10101111 240 table 5?15. scroll step count register (r17) sst7 sst6 sst5 sst4 sst3 sst2 sst1 sst0 scroll step number 00000000 0 (no scroll) 00000001 1 00000010 2 00000011 3 10101101 237 10101110 238 10101111 239 scrolling must be set using the following sequence.
data sheet s15817ej2v0ds 48 pd161623 (1) recommended scroll sequence d 7 ssln setting r15 <1> scroll area start line setting note1 d 0 d 7 sawn setting r16 <2> scroll area line count setting note1 d 0 d 7 sstn setting r17 <3> scroll step count register setting note2 d 0 notes 1. <1> to <2> can be executed in any order. 2. <3> must be executed after <1> and <2> have been set. remark set sstn to 00h to disable the scroll operation. no particular sequence is required for this. cautions 1. if the sum of the values of ssln and sawn is 240 (efh) or over, it is invalid (no scroll operation). 2. set the step number sstn so that it does not exceed the line number sawn. if a value exceeding sawn is set, it will be invalid (no scroll operation).
data sheet s15817ej2v0ds 49 pd161623 (2) scroll setting examples setting a-1 register setting value details of setting value scroll area start line register (r15) 00h sets y address 00h scroll area line count register (r16) efh sets an area of 240 lines setting a-2 register setting value details of setting value scroll area start line register (r15) 00h sets y address 00h scroll area line count register (r16) 77h sets an area of 120 lines setting a-3 register setting value details of setting value scroll area start line register (r15) 78h sets y address 78h scroll area line count register (r16) 77h sets an area of 120 lines setting a-4 register setting value details of setting value scroll area start line register (r15) b4h sets y address b4h scroll area line count register (r16) 77h sets an area of 120 lines
data sheet s15817ej2v0ds 50 pd161623 figure 5?28. display scroll setting examples setting a- 1 scroll area scroll area scroll area scroll area gate source 1 1 240 176 setting a- 2 gate source 1 1 120 121 240 176 setting a- 3 gate source 1 1 240 121 120 181 180 61 60 176 setting a- 4 gate source 1 1 240 176 fixed display area fixed display area fixed display area fixed display area
data sheet s15817ej2v0ds 51 pd161623 (3) scroll setting flowchart example start r15 d 15 d 8 rs d 7 d 0 x0001111 scroll area start line register setting l d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 7 to d 0 are the data for scroll area start line. r16 d 15 d 8 rs d 7 d 0 x0010000 scroll area line count register setting l d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 7 to d 0 are the data for scroll area line count register. r17 d 15 d 8 rs d 7 d 0 x0010001 scroll step count register setting (1 step) l 00000001 r6 d 15 d 8 rs d 7 d 0 x0000110 x address register setting l d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 7 to d 0 depend on application condition. r7 d 15 d 8 rs d 7 d 0 x0000111 y address register setting l d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 7 to d 0 depend on application condition. d 15 d 8 rs d 7 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 display data re-write scrolling area 1 (start) h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 15 to d 0 are display memory data. d 15 d 8 rs d 7 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 display data re-write scrolling area 2 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 15 to d 0 are display memory data. d 15 d 8 rs d 7 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 display data re-write scrolling area n (end) h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 15 to d 0 are display memory data.
data sheet s15817ej2v0ds 52 pd161623 r17 d 15 d 8 rs d 7 d 0 x0010010 scroll step count register setting (2 steps) l 00000001 r6 d 15 d 8 rs d 7 d 0 x0000110 x address register setting l d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 7 to d 0 depend on application condition. r7 d 15 d 8 rs d 7 d 0 x0000111 y address register setting l d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 7 to d 0 depend on application condition. d 15 d 8 rs d 7 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 display data re-write scrolling area 1 (start) h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 15 to d 0 are display memory data. d 15 d 8 rs d 7 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 display data re-write scrolling area 2 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 15 to d 0 are display memory data. d 15 d 8 rs d 7 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 display data re-write scrolling area n (end) h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 caution d 15 to d 0 are display memory data. (repeat) next transaction
data sheet s15817ej2v0ds 53 pd161623 (4) scroll function example scroll area start line register (r15): 3ch scroll area line count register (r16): 77h (a) scroll step count register setting (r17): 00h 181 180 61 60 gate y address source fixed display area fixed display area scroll area 1 1 240 3bh 00h 3ch b3h b4h efh 176 (b) scroll step count register setting (r17): 01h 181 180 61 60 gate y address source 1 1 240 3bh 00h 3dh 3ch b3h b4h efh 176 fixed display area fixed display area scroll area
data sheet s15817ej2v0ds 54 pd161623 (c) scroll step count register setting (r17): 02h 181 180 61 60 gate y address source 1 1 240 3bh 00h 3eh 3ch 3dh b3h b4h efh 176 fixed display area fixed display area scroll area (d) scroll step count register setting (r17): 57h 181 180 61 60 gate y address source 1 1 240 3bh 00h 3ch b2h b3h b4h efh 176 fixed display area fixed display area scroll area
data sheet s15817ej2v0ds 55 pd161623 5.12 stand-by the pd161623 has a stand-by function. input of a stand-by command is acknowledged when the stby bit of the control register 1 (r0) is set to 1. when the stand-by command has been input, the pd161623 is forcibly placed in the v ss display status, and scans the frame being display to the end. when scanning is complete, all gate outputs are turned on, the charge of the pixel on the tft panel is decreased to 0, and the output stage amplifier and internal oscillator are stopped. the stand-by function is valid for only the source driver ic; the gate ic ( pd161641) and power ic ( pd161660) connected to the pd161623 are not controlled by this function. after executing the stand-by command, therefore, execute commands that turn off the regulator for the gate ic and power ic an turn off the dc/dc converter. when the stand-by status is released, turn on the dc/dc converter and the regulator of the gate ic and power ic, and then issue an ordinary operation command (stby = 0), in the reverse order to which the stand-by command was input. (1) stand-by sequence operating status (normal display) r0 d 15 to d 0 control register 1 rs d 15 d 7 d 8 d 0 00000000 control register 1 setting l xxd 5 0 1 000 d 7 : don?t care d 6 : don?t care d 4 : normal display mode (not partial display mode) d 3 : stand-by on d 2 : 65,000-color display mode d 1 : normal power mode d 5 is set in accordance with the usage conditions. the source output is automatically fixed to the v ss level by stand- by, so d 7 and d 6 can be set to any value. wait time 1 (t oe2rg ) at least one frame period r25 d 15 to d 0 power supply control register 1 rs d 15 d 7 d 8 d 0 00011001 power supply control register 1 setting l xd 6 d 5 d 4 d 3 x 0 1 d 6 to d 3 are set in accordance with the usage conditions. d 1 : power supply ic regulator off d 0 : dc/dc converter on wait time 2 (t rpdd ) although a setting of 0 ns has no negative effect in terms of the device, be sure to finalize the timing after sufficient evaluation with the lcd module.
data sheet s15817ej2v0ds 56 pd161623 r25 d 15 to d 0 power supply control register 1 rs d 15 d 7 d 8 d 0 00011001 power supply control register 1 setting l xd 6 d 5 d 4 d 3 x0 0 d 6 to d 3 are set in accordance with the usage conditions. d 2 : gate driver regulator off d 1 : power supply ic regulator off d 0 : dc/dc converter off stand-by setting completed (2) stand-by release sequence stand-by status r0 d 7 to d 0 control register 1 rs d 15 d 7 d 8 d 0 xxxxxxxx control register 1 setting l 1 0d 5 0 0 000 d 7 : all data ?1? output (normally white: white output) d 6 : normal display d 4 : normal display mode (not partial display mode) d 3 : normal mode (stand-by release) d 2 : 65,000-color display mode d 1 : normal power mode d 5 is set in accordance with the usage conditions. r25 d 15 to d 0 power supply control register 1 rs d 15 d 7 d 8 d 0 00011001 power supply control register 1 setting l xd 6 d 5 d 4 d 3 x0 1 d 6 to d 3 is set in accordance with the usage conditions. d 1 : power supply ic regulator off d 0 : dc/dc converter on wait time 1 (t ddrp ) t ddrp is the output stable period of the dc/dc converter. although a setting of about 50 ms is the target, be sure to finalize the timing after sufficient evaluation with the lcd module. r25 d 7 to d 0 power supply control register 1 rs d 15 d 7 d 8 d 0 00011001 power supply control register 1 setting l xd 6 d 5 d 4 d 3 0 1 1 d 6 to d 3 is set in accordance with the usage conditions. d 1 : power supply ic regulator on d 0 : dc/dc converter on wait time 2 (t rprg ) t rprg is the output stable period of the dc/dc converter. although a setting of about 20 ms is the target, be sure to finalize the timing after sufficient evaluation with the lcd module.
data sheet s15817ej2v0ds 57 pd161623 r0 d 7 to d 0 control register 1 rs d 15 d 7 d 8 d 0 00000000 control register 1 setting l 0 0d 5 0 0 000 d 7 : normal display (all data ?1? output display on) d 6 : normal display d 4 : normal display mode (not partial display mode) d 3 : normal mode (stand-by release) d 2 : 65,000-color display mode d 1 : normal power mode d 5 is set in accordance with the usage conditions. next transaction
data sheet s15817ej2v0ds 58 pd161623 6 reset if the /reset input becomes l or the reset command is input, the internal timing generator is initialized. the reset command will also initialize each register to its default value. these default values are listed in the table below. register rn /reset pin note1 reset command default value control register 1 r0 x o a0h control register 2 r1 x o 00h data supplement register r4 x o 00h data access control register r5 x o 00h x address register r6 x o 00h y address register r7 x o 00h min. ? x address register r8 x o 00h max. ? x address register r9 x o 00h min. ? y address register r10 x o 00h min. ? y address register r11 x o 00h display size setting register r13 x o 00h scroll area start line register r15 x o 00h scroll area line count register r16 x o 00h scroll step count register r17 x o 00h partial off area color register r19 x o 00h partial 1 display area start line register r20 x o 00h partial 2 display area start line register r21 x o 00h partial 1 display area line count register r22 x o 00h partial 2 display area line count register r23 x o 00h power supply control register 1 r25 x o 00h power supply control register 2 r26 x o 00h vcom output center value setting register r29 x o 00h output stage capacity setting register r30 x o 00h -reference-voltage generator capacity setting register r31 x o 00h -contrast value setting register 1 r36 x o 00h -contrast value setting register 2 r37 x o 00h -contrast value setting register 3 r38 x o 00h -contrast value setting register 4 r39 x o 00h pre-charge direction setting data register r40 x o 00h -correction input disconnect register r42 x o 00h calibration register note2 r45 x o 01h pre-charge period supplement pulse setting register r46 x o 06h output port register r49 x o 00h interface operating voltage setting register r114 x o 00h internal logic operating voltage setting register r115 x o 00h test mode x o 00h remark o: default value set, x: default value not set notes 1. the internal counters are initialized only by a reset from the /reset pin. be sure to perform reset via the /reset pin at power application. 2. the following value is set as the calibration setting time, t cal , in a reset by reset command. t cal = 1/f osc x 37
data sheet s15817ej2v0ds 59 pd161623 7. command 7.1 command list display data access data bit db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 ram access rs r/w db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 18-bit parallel interface d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 display data read 1 1 1 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 display data write 1 1 0 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 16-bit parallel interface (1-pixel/16-bit mode [dtx=l]) hi-z hi-z d 17 d 16 d 15 d 14 d 13 d 11 d 10 display data read 2 1 1 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ?? d 17 d 16 d 15 d 14 d 13 d 11 d 10 display data write 2 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 16-bit parallel interface (1-pixel / 18-bit mode [dtx=h]) hi-z hi-z ?0? ?0? ?0? ?0? ?0? ?0? ?0? display data read 3 1 1 d 17 (d 8 ) d 16 (d 7 ) d 15 (d 6 ) d 14 (d 5 ) d 13 (d 4 ) d 12 (d 3 ) d 11 (d 2 ) d 10 (d 1 ) d 9 (d 0 ) hi-zhi-zxxxxxxx display data write 3 1 0 d 17 (d 8 ) d 16 (d 7 ) d 15 (d 6 ) d 14 (d 5 ) d 13 (d 4 ) d 12 (d 3 ) d 11 (d 2 ) d 10 (d 1 ) d 9 (d 0 ) common status read 0 1 remark hi-z: high impedance, x: invalid data caution when the 16-bity parallel interface is used in 1-pixel/18-bit mode (dtx = h), data access of two words per pixel is required.
data sheet s15817ej2v0ds 60 pd161623 18-bit parallel interface mode, db 17 , db 16 = 0 (1/3) data bit db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 rn register rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 00000000 r0 control register 1 0 0 disp1 disp0 adc dty stby color lpm gsm 00000001 r1 control register 2 0 0 vsel gsel 00ltsinv 00000010 r2 ? 00 00000011 r3 reset register 0 0 res 00000100 r4 data supplement register 0 0 cd12 cd0 00000101 r5 data access control register 0 0 bstr was 000 00000110 r6 x address register 0 0 xa 7 xa 6 xa 5 xa 4 xa 3 xa 2 xa 1 xa 0 00000111 r7 y address register 0 0 ya 7 ya 6 ya 5 ya 4 ya 3 ya 2 ya 1 ya 0 00001000 r8 min. ? x address register 0 0 xmin7 xmin6 xmin5 xmin4 xmin3 xmin2 xmin1 xmin0 00001001 r9 max. ? x address register 0 0 xmax7 xmax6 xmax5 xmax4 xmax3 xmax2 xmax1 xmax0 00001010 r10 min. ? y address register 0 0 ymin7 ymin6 ymin5 ymin4 ymin3 ymin2 ymin1 ymin0 00001011 r11 max. ? y address register 0 0 ymax7 ymax6 ymax5 ymax4 ymax3 ymax2 ymax1 ymax0 00001100 r12 ? 00 00001101 r13 display size setting register 0 0 ngo0 00001110 r14 ? 00 00001111 r15 scroll area start line register 0 0 ssl 7 ssl 6 ssl 5 ssl4 ssl3 ssl2 ssl1 ssl0 00010000 r16 scroll area line count register 0 0 saw7 saw6 saw5 saw4 saw3 saw2 saw1 saw0 00010001 r17 scroll step count register 0 0 sst7 sst6 sst5 sst4 sst3 sst2 sst1 sst0 00010010 r18 ? 00 00010011 r19 partial off area color register 0 0 pgr pgg pgb 00010100 r20 partial 1 display area start line register 00 p1sl7 p1sl6 p1sl5 p1sl4 p1sl3 p1sl2 p1sl1 p1sl0 00010101 r21 partial 2 display area start line register 00 p2sl7 p2sl6 p2sl5 p2sl4 p2sl3 p2sl2 p2sl1 p2sl0
data sheet s15817ej2v0ds 61 pd161623 18-bit parallel interface mode, db 17 , db 16 = 0 (2/3) data bit db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 rn register rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 00010110 r22 partial 1 display area line count register 00 p1aw7 p1aw6 p1aw5 p1aw4 p1aw3 p1aw2 p1aw1 p1aw0 00010111 r23 partial 2 display area line count register 00 p2aw7 p2aw6 p2aw5 p2aw4 p2aw3 p2aw2 p2aw1 p2aw0 00011000 r24 ? 00 00011001 r25 power supply control register 1 0 0 bgrs vce vcd2 pvcom rgonp dcon 00011010 r26 power supply control register 2 0 0 vcd12 vcd11 00011011 r27 ? 00 00011100 r28 ? 00 00011101 r29 vcom output center value setting register 00 ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0 00011110 r30 output stage capacity setting register 00 bpl ci2 ci1 ci0 vcomc sf2 sf1 sf0 00011111 r31 -reference-voltage generator capacity setting register 00 whp wi2 wi1 wi0 bhp bi2 bi1 bi0 00100000 r32 ? 00 00100001 r33 ? 00 00100010 r34 ? 00 00100011 r35 ? 00 00100100 r36 -contrast value setting register 1 00 gph7 gph6 gph5 gph4 gph3 gph2 gph1 gph0 00100101 r37 -contrast value setting register 2 00 gnh7 gnh6 gnh5 gnh4 gnh3 gnh2 gnh1 gnh0 00100110 r38 -contrast value setting register 3 00 gpl7 gpl6 gpl5 gpl4 gpl3 gpl2 gpl1 gpl0 00100111 r39 -contrast value setting register 4 00 gnl7 gnl6 gnl5 gnl4 gnl3 gnl2 gnl1 gnl0 00101000 r40 pre-charge direction setting data register 00 rdtp3 rdtp2 rdtp1 rdtp0 rdtn3 rdtn2 rdtn1 rdtn0 00101001 r41 ? 00 00101010 r42 -correction input disconnect register 00 ghsw 00101011 r43 ? 00
data sheet s15817ej2v0ds 62 pd161623 18-bit parallel interface mode, db 17 , db 16 = 0 (3/3) data bit db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 rn register rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 00101100 r44 ? 00 00101101 r45 calibration register 0 0 oc 00101110 r46 pre-charge period supplement pulse setting register 00 plim6 plim5 plim4 plim3 plim2 plim1 plim0 00101111 r47 ? 00 00110000 r48 ? 00 00110001 r49 output port register 0 0 op7 op6 op5 op4 op3 op2 op1 op0 00110010 r50 ? 00 00110011 r51 ? 00 00110100 r52 ? 00 00110101 r53 ? 00 00110110 r54 ? 00 00110111 r55 ? 00 00111000 r56 ? 00 00111001 r57 ? 00 00111010 r58 ? 00 00111011 r59 ? 00 00111100 r60 ? 00 00111101 r61 ? 00 00111110 r62 ? 00 00111111 r63 ? 00 01110010 r114 interface operating voltage setting register 00 rtsc1 rtsc0 01110011 r115 internal logic operating voltage setting register 00 rtsl1 rtsl0
data sheet s15817ej2v0ds 63 pd161623 7.2 command explanation (1/8) register bit symbol function d 7 disp1 this command performs the same output as when all data is 1, independently of the internal ram data (white display in the case of normally white). this command is executed, after it has been transferred, when the next line isoutput. 0: normal operation 1: ignores data of ram and outputs all data as 1. disp1 takes precedence over disp0. when disp1 = h, disp0 = h is ignored. d 6 disp0 this command performs the same output as when all data is 0, independently of the internal ram data (black display in the case of normally white). this command is executed, after it has been transferred, when the next line is output. 0: normal operation 1: ignores data of ram and outputs all data as 0. d 5 adc column address direction this command can be used to select the direction of source driver output. for more detail, refer to 5.2.3 column address circuit . d 4 dty this pin selects the partial function. when the partial function s selected in the 260,000-color mode, set the partial-off area-color selection register (r27) to 00h. in the 8-color mode, the partial off area color can be set to any value from 00h to 07 h. the power consumption cannot be reduced with the partial function. to reduce the power consumption, select the 8-color mode. this command is executed following transfer from the time the next line data is output. 0: normal display mode 1: partial display mode d 3 stby this bit selects the stand-by function. when the stand-by function is selected, a display off operation is executed and the amplifiers at each output stage and the operation of internal oscillation circuit are stopped. however, stand-by control cannot be performed for the power supply ics ( pd161660 and others) connected to pd161623. therefore, after executing the stand-by function using this bit, set both the regulator for the power supply ic to off and set the dc/dc converter to off. for the sequence, refer to the data sheets of the power supply ic. note that when releasing stand-by, perform the opposite operation, i.e., after setting the dc/dc converter to on and setting the regulators of the power supply ic to on, execute the normal operation command. 0: normal operation 1: stand-by function (display read off from ram, stop both osc and vcom, display off = entire data is output as 1) r0 d 2 color this pin switches the 260,000-color mode and the 8-color mode. when the 8-color mode is selected, low power supply can be selected in order to stop the amplifier at each output stage. in the 8-color mode, the value of the msb of the internal ram data is used as the color data. this command is executed following transfer from the time the next line data is output. 0: 260,000-color mode (18-bits/pixels) 1: 8-color mode (3-bits/pixels)
data sheet s15817ej2v0ds 64 pd161623 (2/8) register bit symbol function d 1 lpm this bit is used when setting the power supply ic ( pd161660) to the low-power mode. when the low-power mode is selected, the lpmp pin signal change from low to high (output changes immediately following command execution.). the lpmp pin must be connected to the lpm pin of the power supply ic. 0: normal 1: low power mode r0 d 0 gsm sets output of the gate scanning signal during partial display. when 1 is selected, gate scanning of the line set in the partial non-display area is stopped. 0: normal mode 1: stops gate scanning in partial non-display area d 5 vsel sets the potential of the pre-charge output of the lcd driver. the maximum/minimum output potential of the pre-charge output is: 0: maximum output level of internal -output adjustment circuit (uses vph, vnh, vpl, vnl) 1: partial voltage (outputs v s and v ss ) if vsel = 0, v s or v ss is automatically output as the pre-charge output. d 4 gsel sets the maximum/minimum output voltage of the ? correction register. if the internal -output adjustment circuit is selected, the maximum/minimum output potential of the -correction register is: 0: supply voltage (outputs v s and v ss ). 1: voltage of internal -output adjustment circuit (uses vph, vnh, vpl, vnl) 8-color mode (3 bits/pixels) d 1 lts selects set time of calibration. the calibration function adjusts the frame frequency by setting time of one line. this command can select the set time of a line from the following: 0: 1 line time = t cal 1: 1 line time = t cal x 2 (t cal : calibration set time1 = 1 frame frequency number of displayed lines) r1 d 0 inv this bit selects between the line inversion function and the frame inversion function. the mode selected by this command is executed from the start of the next scan after the gate scan in progress when this command was executed has completed 176 lines. 0: line inversion 1: frame inversion r3 d 0 res command reset function. be sure to execute this bit after power on. command reset automatically clears this bit following execution (res = 1). therefore, it is not necessary to set 0 (select normal operation) again by software. moreover, since the time required for the value of this bit to change (1 0) following command reset execution is extremely short, it is not necessary to secure time until the next command is set following command reset setting. 0: normal operation 1: command reset d 1 cd12 r4 d 0 cd0 when using the 1-pixel/16-bit mode (dtx = l) and the 18-bit parallel interface, when the data from the cpu is stored in the display ram, this register supplements data (display ram data: d 12 , d 0 ) for the two bits of deficient data using the set data and writes 18-bit data to the display ram. for details, refer to 5.1.2 selection of data transfer mode . cd12: display ram data d 12 is supplemented cd0: display ram data d 0 is supplemented
data sheet s15817ej2v0ds 65 pd161623 (3/8) register bit symbol function d 6 bstr sets the write mode for writing data to the display ram. if the high-speed ram write mode is selected, data is written to the display ram in 2-pixel units inside the pd161623. when selecting the high-speed ram write mode, be sure to write data to the display ram in 2-pixel units. 0: normal write mode (18-bit access: 4 mhz max.) 1: high-speed ram write mode (36-bit access: 8 mhz max.) r5 d 4 was window access mode setting when the window access mode is set, the address is incremented/decremented only in the range set by the min. ? x address setting register (r8), max. ? x address setting register (r9), min. ? y address setting register (r10), and max. ? y address setting register (r11). 0: normal operation 1: window access mode r6 d 7 to d 0 xan this register sets the x address of the display ram. set a value between 00h and afh. r7 d 7 to d 0 yan this register sets the y address of the display ram. set a value between 00h and efh. r8 d 7 to d 0 xminn sets the minimum value of the x address in the window access mode. the x address is incremented up to the maximum value set by the max. ? x address register (r9), and then initialized to the address value set by this command. set this register to 00h to aeh. r9 d 7 to d 0 xmaxn sets the maximum value of the x address in the window access mode. the x address is incremented up to the maximum value set by the min. ? x address register (r8), and then initialized to the address value set by this command. set this register to 01h to afh. r10 d 7 to d 0 yminn sets the minimum value of the t address in the window access mode. the y address is incremented up to the maximum value set by the max. ? y address register (r11), and then initialized to the address value set by this command. set 00h to eeh. r11 d 7 to d 0 ymaxn sets the maximum value of the y address in the window access mode. the y address is incremented up to the address value set by this command, and then initialized to the minimum address value set by the min. ? y address register (r10). set 01h to efh. selects output number (gate scan) of gate driver. ngo0 gate output number 0 240-gate outputs 1 220-gate outputs r13 d 0 ngo0 r15 d 7 to d 0 ssln scroll area start line register (00h to efh) when the screen is scrolled, the screen of the number of lines set by the scroll area line count register (r16) is scrolled up by the number of steps set by the scroll step count register (r17), starting from the line set by this command. r16 d 7 to d 0 sawn scroll area line count register (00h to efh) when the screen is scrolled, the screen of the number of lines set by this command is scrolled up by the number of steps set by the scroll step count register (r17), starting from the line set by the scroll area start line register (r15).
data sheet s15817ej2v0ds 66 pd161623 (4/8) register bit symbol function r17 d 7 to d 0 sstn scroll step count register (00h to efh) when the screen is scrolled, the screen of the number of lines set by the scroll area line count register (r16) and the scroll step count register (r17) is scrolled up by the number of steps set by this command. note that because this command is invalid in the partial display mode, the scroll function cannot be used. d 2 pgr d 1 pgg r19 d 0 pgb partial off area color register sets the color of the screen other than the partial display area during partial display (r0: dty = 1). one of eight colors can be selected (rgb: 1 bit each) as the off color. the relationship between each color data and the bits of this register is as follows. this relationship is not dependent upon the value of adc. pgr: r off= 0, on = 1 pgg: g off= 0, on = 1 pgb: b off= 0, on = 1 r20 d 7 to d 0 p1sln partial1 display area start line register (00h to efh) during partial display (r0: dty = 1), the area starting from the line set by this command and ending as set by the partial 1 display area line count register (r22) is the partial 1 display area. r21 d 7 to d 0 p2sln partial2 display area start line register (00h to efh) during partial display (r0: dty = 1), the area starting from the line set by this command and ending as set by the partial 2 display area line count register (r23) is the partial 2 display area. r22 d 7 to d 0 p1awn partial1 display area line count register (00h to efh) an area starting from the line set by the partial 1 display area start register (r20) and ending as set by this command is the partial 1 display area. if this register is 0, the values of the partial 2 display area start line register (r29) and the partial 2 display area line count register (r31) are not valid. r23 d 7 to d 0 p2aw n partial 2 display area line count register (00h to efh) an area starting from the line set by the partial 2 display area start register (r21) and ending as set by this command is the partial 2 display area. if the partial 1 display area line count register is 0, the values of the partial 2 display area start line register (r21) and partial 2 display area line count register (r23) are not valid. d 6 bgrs this pin selects whether to use the internal power supply or an external power supply (input from the brgin pin) for generation the common center voltage output from the vcom pin. 0: the internal power supply is selected as the vcom power supply 1: input from the external power supply bgrin is selected as the bcom power supply d 5 vce selects the v o output level of the power supply ic ( pd161660). the v ce pin of the pd161623 and the v ce pin of the power supply ic must be connected. 0: the vo high-level booster voltage level is v dd2 minus 1 level 1: the vo high-level booster voltage level is the same level as v dd2 d 4 vcd2 selects the v dd2 output level of the power supply ic ( pd161660). the v cd2 pin of the pd161623 and the v cd2 pin of the power supply ic must be connected. 0: v dd2 = v cd 2 1: v dd2 = v cd 3 r25 d 3 pvcom selects the voltage supplied to the vcom output circuit. 0: vcom output circuit power supply, v dd2 1: vcom output circuit power supply, v s
data sheet s15817ej2v0ds 67 pd161623 (5/8) register bit symbol function d 1 rgonp switches the internal dc/dc converter of the power supply ic ( pd161660) on/off. when off is selected, a low level is output from the rgonp pin, and when on is selected, a high level is output from the rgonp pin. the rgonp pin of this ic and the rgonp pin of the power supply ic must be connected. 0: regulators of power supply ic (v t , v s ) are off 1: regulators of power supply ic (v t , v s ) are on r25 d 0 dcon switches the internal dc/dc converter of the power supply ic ( pd161660) on/off. when off is selected, a low level is output from the dcon pin, and when on is selected, a high level is output from the dcon pin. the dcon pin of the pd161623 and the dconp pin of the power supply ic must be connected. 0: dc/dc converter is off 1: dc/dc converter is on d 1 vcd12 r26 d 0 vcd11 performs booster control for the dc/dc converter in the power supply ic ( pd161660) the data set with this bit is output from the vcd11 pin and the vcd12 pin. the vcd11 pin and vcd12 pin of the pd161623 must be connected to the vcd11 pin and the vcd12 pin of the power supply ic. vcd12, vcd11 = 0, 0: v dd2 = v dc 4 = 0, 1: v dd2 = v dc 5 = 1, 0: v dd2 = v dc 6 = 1, 1: v dd2 = v dc 7 r29 d 7 to d 0 evn sets the d/a converter circuit used to adjust the voltage of the reference voltage generator circuit (vbgr) input to the voltage regulator that sets the center value of the panel common drive output. the d/a converter divides the constant voltage generated by the reference voltage generator (vbgr) by 256, and one level can be selected between vbgr and v ss by setting this command. for more detail, refer to 5.5 common adjustment circuit and 5.8 d/a converter circuit . d 7 bpl switched the capacity of the -correction circuit reference voltage generation amplifiers on the side not being used (vph, vpl, vnh, vnl) to the minimum value based on the polarity inversion timing in order to reduce the current consumption. determine the amplifier capacity after sufficient evaluation with the actual tft panel to be used. 0: normal 1: reference voltage generation amplifier capacity switch drive sets the bias current of the amplifier for setting the panel?s common drive waveform center value (vcom), as shown in the table below. determine the amplifier capacity after sufficient evaluation with the actual tft panel to be used. ci2 ci1 ci0 vcom center value setting amplifier bias current value 000 0.20 a 001 0.50 a 010 0.10 a 011 0.05 a 100 1.00 a 101 1.50 a 110 2.00 a 111 3.00 a r30 d 6 to d 4 cin
data sheet s15817ej2v0ds 68 pd161623 (6/8) register bit symbol function d 3 vcomc selects whether to use the amplifier for setting the panel?s common drive waveform center value (vcom) or not. this amplifier can be used under conditions such as when an external common drive circuit is being used. 0: vcom amplifier operating 1: vcom amplifier stopped sets the capacity of the source output (y 1 to y 528 ), as shown in the table below. determine the output capacity after sufficient evaluation with the actual tft panel to be used. sf2 sf1 sf0 source output bias current value 000 0.20 a 001 0.15 a 010 0.25 a 011 0.10 a 100 0.20 a 101 0.30 a 110 0.40 a 111 0.05 a r30 d 2 to d 0 sfn d 7 whp sets the output mode of the reference voltage generator amplifier for setting the white level of the positive-polarity and negative-polarity sides (when vpl and vnl are normally white), as shown below. determine the amplifier capacity after sufficient evaluation with the actual tft panel to be used. 0: normal mode 1: high-power mode (output stage capacity: twice that of normal mode) sets the output bias current of the reference voltage generator amplifier for setting the white level of the positive-polarity and negative-polarity sides (when vpl and vnl are normally white), as shown below. wi2 wi1 wi0 amplifier bias current 000 0.20 a 001 0.50 a 010 0.10 a 011 0.05 a 100 1.00 a 101 1.50 a 110 2.00 a 111 3.00 a d 6 to d 4 win r31 d 3 bhp sets the output mode of the reference voltage generator amplifier for setting the black level of the positive-polarity and negative-polarity sides (when vph and vnh are normally white), as shown below. determine the amplifier capacity after sufficient evaluation with the actual tft panel to be used. 0: normal mode 1: high-power mode (output stage capacity: twice that of normal mode)
data sheet s15817ej2v0ds 69 pd161623 (7/8) register bit symbol function sets the output bias current of the reference voltage generator amplifier for setting the black level of the positive-polarity and negative-polarity sides (when vph and vnh are normally white), as shown below. determine the amplifier capacity after sufficient evaluation with the actual tft panel to be used. bi2 bi1 bi0 amplifier bias current 000 0.20 a 001 0.50 a 010 0.10 a 011 0.05 a 100 1.00 a 101 1.50 a 110 2.00 a 111 3.00 a r31 d 2 to d 0 bin r36 d 7 to d 0 gphn sets the voltage value of the black level of positive polarity. for more detail, refer to 5.9 -curve correction power supply circuit . r37 d 7 to d 0 gnhn sets the voltage value of the white level of negative polarity. for more detail, refer to 5.9 -curve correction power supply circuit . r38 d 7 to d 0 gpln sets the voltage value of the white level of positive polarity. for more detail, refer to 5.9 -curve correction power supply circuit . r39 d 7 to d 0 gnln sets the voltage value of the white level of positive polarity. for more detail, refer to 5.9 -curve correction power supply circuit . sets the data value at which the pre-charge direction is switched during positive-polarity drive. the value set to rdtpn corresponds to the higher 4bits of display ram data db n (6 bits for each of rfb), as shown below. rdtp3 rdtp2 rdtp1 rdtp0 dot 1 (r) d 17 d 16 d 15 d 14 dot 2 (g) d 11 d 10 d 9 d 8 dot 3 (b) d 5 d 4 d 3 d 2 d 7 to d 4 rdtpn sets the data value at which the pre-charge direction is switched during negative-polarity drive. the value set to rdtnn corresponds to the higher 4 bits of display ram data db n (6 bits for each of rgb), as shown below. rdtn3 rdtn2 rdtn1 rdtn0 dot 1 (r) d 17 d 16 d 15 d 14 dot 2 (g) d 11 d 10 d 9 d 8 dot 3 (b) d 5 d 4 d 3 d 2 r40 d 3 to d 0 rdtnn r42 d 0 ghsw controls the -correction voltage input pins (v 0 to v 5 ) and the switch for connecting the pd161623 internal -correction resistor. 0: switch off (disconnected) 1: switch on (connected) r45 d 0 oc this bit is used for calibration. the time from calibration start command execution until calibration stop command execution becomes the time for 1 line. 0: calibration stop 1: calibration start
data sheet s15817ej2v0ds 70 pd161623 (8/8) register bit symbol function r46 d 6 to d 0 plimn sets the clock count for the pre-charge period. the value written to this register is set as the clock count (1/f ocs ) of the pre-charge period. for details, refer to 5.4.1 dispaly timing r49 d 7 to d 0 opn output port (op 7 to op 0 ) write when after the output port register is specified in the index register, writing to the output port register is performed, the values written to the op 7 to op 0 pins are output. selects the optimum internal circuit operation based on the operating voltage of the interface circuits. to set by this register, we recommend as follow setting. rtsc1 rtsc0 01 r114 d 1 , d 0 rtscn caution always set this register and internal logic operating voltage setting register (r115) to the same value. selects the optimum internal circuit operation based on the operating voltage of the internal logic circuits. to set by this register, we recommend as follow setting. rtsc1 rtsc0 01 r115 d 1 , d 0 rtsln caution always set this register and interface operating voltage setting register (r114) to the same value.
data sheet s15817ej2v0ds 71 pd161623 8. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol ratings unit power supply voltage v s ?0.5 to +6.5 v power supply voltage v dd1 ?0.5 to v dd2 + 0.5 v power supply voltage v dd2 ?0.5 to +4.0 v power supply voltage for -curve correction v 0 to v 5 ?0.5 to v s + 0.5 v input voltage v i ?0.5 to v dd2 + 0.5 v input current i i 10 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol min. typ. max. unit v s 4.3 5.0 5.5 v v dd1 1.7 1.8 v dd2 v power supply voltage v dd2 2.5 2.7 3.6 v v i1 note1 0v dd2 v input voltage v i2 note2 0v dd1 v notes 1. pins of v dd1 power supply system: psx, c86, t out0 to t out17 , op 0 to op 7 , lpmp, goe 1 , goe 2 , gstb, gclk, dcon, rgonp, v cd11 , v cd12 , v cd2 , v ce , osc sel , test in , tstrtst, tstvihl, tosci 2. pins of v dd2 power supply system: /cs, /rd (e), /wr (r,/w), d 0 to d 17 , rs, /reset, osc in
data sheet s15817ej2v0ds 72 pd161623 electrical specifications (unless otherwise specified, t a = ? 40 to +85 c, v dd1 = 1.7 v to v dd2 , v dd2 = 2.5 to 3.6 v, v s = 4.3 to 5.5 v) parameter symbol condition specification unit min. typ. note1 max. high level input voltage v ih1 v dd2 0.8 v dd2 v v ih2 v dd1 0.8 v dd1 v low level input voltage v il1 v dd2 0.2 v dd2 v v il2 v dd1 0.2 v dd1 v high level output voltage v oh1 v dd2 , i out = ?100 a 0.9 v dd2 v v oh2 v dd1 , i out = ?1 ma 0.8 v dd1 v v oh3 vcout1, vcout2, i out = ?100 a 0.9 v v low level output voltage v ol1 v dd2 , i out = 100 a 0.1 v dd2 v v ol2 v dd1 , i out = 1 ma 0.2 v dd1 v v ol3 vcout1, vcout2, i out = 100 a 0.1 v s v vcom output voltage v comh i source = 100 a vcom ? 0.3 v v coml i sink = ?100 a vcom ? 0.3 v high level input current i ih1 except d 0 to d 17 1 a low level input current i il1 except d 0 to d 17 ?1 a high level leakage current i lih d 0 to d 17 10 a low level leakage current i lil d 0 to d 17 ?10 a high level driver output current i voh v x = 3.5 v, v out = 4.5 v, v s = 5.0 v note2 ? 100 a low level driver output current i vol v x = 2.0 v, v out = 1.0 v, v s = 5.0 v note2 150 a vcom common output voltage fluctuation parameter ? v com ? 10 10 % current consumption i dd1 v dd1 (when non-access cpu) 0.1 2 a i dd2 v dd2 (when non-access cpu) 200 350 a i stby stand-by mode, v dd2 pin 0.1 10 a i s 260,000-color mode note3 650 1250 a 8-color mode note3 50 200 a i voh v out = v s ? 0.1 v, v s = 5.0 v note2 ?5 a driver output current (pre-charge) i vol v out = v ss + 0.1 v, v s = 5.0 v note2 2 a ? v o1 v o = 1.3 v to v s ? 1.3 v ?20 +20 mv output voltage deviation ? v o2 v o = 0.3 to 1.3 v v o = v s ? 1.3 v to v s ? 0.3 v ?30 +20 mv output voltage period v o input data: h to h v ss + 0.2 v s ? 0.2 v notes 1. typ. values are reference values when t a = 25 c 2. v x refers to the output voltage of analog output pins y 1 to y 528 . v out refers to the voltage applied to analog output pins y 1 to y 528 . 3. frame frequency: 60 hz, line inversion mode select, dot checkerboard input pattern, no load.
data sheet s15817ej2v0ds 73 pd161623 switching characteristics (unless otherwise specified, t a = ? 40 to +85 c, v dd1 = 1.7 v to v dd2 , v dd2 = 2.5 to 3.6 v, v s = 4.3 to 5.5 v) v out t plh1 v o max. ? 200 mv goal voltage +t.b.d. mv pre-charge period driver output period t phl1 t phl2 t plh2 v o min. +200 mv goal voltage +t.b.d. mv parameter symbol condition min. typ. note max. unit t plh1 v o max. ?200 mv 7.0 s driver output delay time 1 (pre-charge period) t phl1 v o min. +200 mv 9.5 s t plh2 50 s driver output delay time 2 (driver output period) t phl2 v s = 5.0 v, 4 k ? +27 pf pre-charge completed goal voltage 52 s note typ. values are reference values when t a = 25 c.
data sheet s15817ej2v0ds 74 pd161623 ac characteristics (unless otherwise specified, t a = ? 40 to +85 c, v dd1 = 1.7 v to v dd2 , v dd2 = 2.5 to 3.6 v, v s = 4.3 to 5.5 v) (a) i80 series cpu interface t as8 t ah8 t cclw , t cclr t cyc8 t cchr , t cchw t dh8 t ds8 t acc8 t oh8 rs /cs /wr, /rd d 0 to d 17 (write) d 0 to d 17 (read) t f t r
data sheet s15817ej2v0ds 75 pd161623 when v dd1 = 2.5 to 3.6 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 (normal write mode, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 250 ns control low-level pulse width (/wr) t cclw /wr 120 ns control low-level pulse width (/rd) t cclr /rd 140 ns control high-level pulse width (/wr) t cchw /wr 60 ns control high-level pulse width (/rd) t cchr /rd 80 ns data setup time t ds8 d 0 to d 17 80 ns data hold time t dh8 d 0 to d 17 0ns /rd access time t acc8 d 0 to d 17 , c l = 100 pf 110 ns output disable time t oh8 d 0 to d 17 , c l = 100 pf 10 100 ns note typ. values are reference values when t a = 25 c. remarks 1. the input signal's rise/fall times (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20 to 80% of v dd1 . when v dd1 = 1.7 to 2.5 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 (normal write mode, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 333 ns control low-level pulse width (/wr) t cclw /wr 120 ns control low-level pulse width (/rd) t cclr /rd 160 ns control high-level pulse width (/wr) t cchw /wr 100 ns control high-level pulse width (/rd) t cchr /rd 140 ns data setup time t ds8 d 0 to d 17 100 ns data hold time t dh8 d 0 to d 17 0ns /rd access time t acc8 d 0 to d 17 , c l = 100 pf 150 ns output disable time t oh8 d 0 to d 17 , c l = 100 pf 10 150 ns note typ. values are reference values when t a = 25 c. remarks 1. the input signal's rise/fall times (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20 to 80% of v dd1 .
data sheet s15817ej2v0ds 76 pd161623 when v dd1 = 2.5 to 3.6 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 (high-speed ram write mode, valid only for writing data, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 125 ns control low-level pulse width (/wr) t cclw /wr 60 ns control high-level pulse width (/wr) t cchw /wr 30 ns data setup time t ds8 d 0 to d 17 80 ns data hold time t dh8 d 0 to d 17 0ns note typ. values are reference values when t a = 25 c. remarks 1. the input signal's rise/fall times (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20 to 80% of v dd1 . when v dd1 = 1.7 to 2.5 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 , (high-speed ram write mode, valid only for writing data, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 167 ns control low-level pulse width (/wr) t cclw /wr 60 ns control high-level pulse width (/wr) t cchw /wr 50 ns data setup time t ds8 d 0 to d 17 100 ns data hold time t dh8 d 0 to d 17 0ns note typ. values are reference values when t a = 25 c. remarks 1. the input signal's rise/fall times (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20 to 80% of v dd1 .
data sheet s15817ej2v0ds 77 pd161623 (b) m68 series cpu interface t as6 t ah6 t ewhr , t ewhw t cyc6 t ewlr , t ewlw t dh6 t ds6 t acc6 t oh6 rs /cs e t f t r d 0 to d 17 (write) d 0 to d 17 (read)
data sheet s15817ej2v0ds 78 pd161623 when v dd1 = 2.5 to 3.6 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 (normal mode, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 250 ns data setup time t ds6 d 0 to d 17 80 ns data hold time t dh6 d 0 to d 17 0ns access time t acc6 d 0 to d 17 , c l = 100 pf 110 ns output disable time t oh6 d 0 to d 17 , c l = 100 pf 10 100 ns enable high pulse width read t ewhr e 140 ns write t ewhw e 120 ns enable low pulse width read t ewlr e80ns write t ewlw e60ns note typ. values are reference values when t a = 25 c. remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. when using a fast system cycle time, the rated value range is either (t r + t f ) < (t cyc6 ?t ewlr ?t ewhr ) or (t r + t f ) < (t cyc6 ?t ewlw ?t ewhw ). 2. all timing is rated based on 20 to 80% of v dd1 . when v dd1 = 1.7 to 2.5 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 (normal mode, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 333 ns data setup time t ds6 d 0 to d 17 100 ns data hold time t dh6 d 0 to d 17 0ns access time t acc6 d 0 to d 17 , c l = 100 pf 150 ns output disable time t oh6 d 0 to d 17 , c l = 100 pf 10 150 ns enable high pulse width read t ewhr e 160 ns write t ewhw e 160 ns enable low pulse width read t ewlr e 140 ns write t ewlw e 100 ns note typ. values are reference values when t a = 25 c. remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. when using a fast system cycle time, the rated value range is either (t r + t f ) < (t cyc6 ?t ewlr ?t ewhr ) or (t r + t f ) < (t cyc6 ?t ewlw ?t ewhw ). 2. all timing is rated based on 20 to 80% of v dd1 .
data sheet s15817ej2v0ds 79 pd161623 when v dd1 = 2.5 to 3.6 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 (high-speed ram write mode, valid only for writing data, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 125 ns data setup time t ds6 d 0 to d 17 80 ns data hold time t dh6 d 0 to d 17 0ns enable high pulse width t ewhr e60 ns enable low pulse width t ewlr e30 ns note typ. values are reference values when t a = 25 c. remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. when using a fast system cycle time, the rated value range is either (t r + t f ) < (t cyc6 ?t ewlr ?t ewhr ) or (t r + t f ) < (t cyc6 ?t ewlw ?t ewhw ). 2. all timing is rated based on 20 to 80% of v dd1 . when v dd1 = 1.7 to 2.5 v, v dd2 = 2.5 to 3.6 v, v dd2 v dd1 (high-speed ram write mode, valid only for writing data, r114 = r115 = 01h) parameter symbol condition min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 167 ns data setup time t ds6 d 0 to d 17 100 ns data hold time t dh6 d 0 to d 17 0ns enable high pulse width t ewhr e60 ns enable low pulse width t ewlr e50 ns note typ. values are reference values when t a = 25 c. remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. when using a fast system cycle time, the rated value range is either (t r + t f ) < (t cyc6 ?t ewlr ?t ewhr ) or (t r + t f ) < (t cyc6 ?t ewlw ?t ewhw ). 2. all timing is rated based on 20 to 80% of v dd1 .
data sheet s15817ej2v0ds 80 pd161623 (c) common parameter symbol condition min. typ. note1 max. unit f osc1 internal oscillator, 240 line (ngo = 0) 370 535 850 khz f osc2 internal oscillator, 220 line (ngo = 1) 300 490 760 khz oscillation frequency f osc3 external oscillator, 240 line (ngo = 0), resistance for oscillator r l = 42 k ? 536.2 note5 khz t cal1 (f frame01 ) internal oscillator, 240 line (ngo = 0), note2 29.7 (139.6) 69.1 (60) 162.4 (25.6) s (hz) calibration setting time (frame frequency) t cal2 (f frame02 ) internal oscillator, 220 line (ngo = 1), note2 36.7 (123.4) 69.1 (60) 181.6 (24.9) s (hz) f frame1 uncalibrated 406095hz f frame2 calibrated note3 54 60 66 hz frame frequency f frame3 calibrated note4 56 60 64 hz f oscin1 external oscillator, 240 line (ngo = 0) 535 khz input oscillation frequency f oscin2 external oscillator, 220 line (ngo = 1) 490 khz reset pulse width at power on t vr v dd2 or v dd1 to /reset 100 ns reset pulse width t rw 100 ns reset time t r /reset to interface operation 100 ns notes 1. typ. values are reference values when t a = 25 c. 2. the relationship between the frame frequency and the calibration setting time is as follows. f frame01 = f frame02 = 3. measured at t a = ?40 to +85 c, after calibration at frame frequency = 60 hz, t a = 25 c exactly. 4. measured at 5 c, after calibration at frame frequency = 60 hz exactly. 5. this value is a reference value in some measurement conditions. note that be able to use and obtain after a real board's fully estimating. 1 t cal x 241 1 t cal x 221
data sheet s15817ej2v0ds 81 pd161623 9. pd161623, 161641, and 161660 connection diagram example connection diagram examples for the pd161623, 161641, and 161660 are shown below. pd161623 pd161660 pd161641 tft-lcd panel 176 x rgb x 240 cpu v dd 1.7 v to v dd2 a n v t v o /cs /rd (e) /wr (r,/w) d 0 to d 17 reset /cs /rd (e) /wr (r,/w) d 0 to d 17 reset rs v dd2 v dd1 v s dcon rgonp v ce v cd11 v cd12 v cd2 lpmp gclk gstb goe 1 goe 2 vcomr vcom vcout1 v ss y 2 y 528 y 527 y 1 v cc1 dcon rgonp v ce v cd11 v cd12 v cd2 lpmp v s v dc v ss 2.5 to 5.5 v 2.5 to 3.6 v gnd(0 v) clk stvr(stvl) oe 1 v cc1 v ee v t oe 2 o 1 o 2 o 240 v ss common sb fbrsel
data sheet s15817ej2v0ds 82 pd161623 10. example of pd161623 and cpu connection examples of pd161623 and cpu connection are shown below. in the example below, rs pin control in parallel interface mode is described for the case when the least significant bit of the address bus is being used. a0 /cs /rd v dd (1) i80 series format d 0 to d 17 pd161623 v ss /wr /reset rs /cs /rd v dd1 d 0 to d 17 v ss /wr /reset v dd2 cpu (2) m68 series format a0 /cs r, /w v dd d 0 to d 17 pd161623 v ss e /reset rs /cs v dd1 d 0 to d 17 v ss e /reset v dd2 cpu r, /w
data sheet s15817ej2v0ds 83 pd161623 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd161623 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of july 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

▲Up To Search▲

Price & Availability of UPD161623

	To Download UPD161623 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .